1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Sunxi A31 Power Management Unit register definition. 4 * 5 * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> 6 * http://linux-sunxi.org 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * Berg Xing <bergxing@allwinnertech.com> 9 * Tom Cubie <tangliang@allwinnertech.com> 10 */ 11 12 #ifndef _SUNXI_PRCM_H 13 #define _SUNXI_PRCM_H 14 15 #define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) 16 #define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) 17 #define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) 18 #define PRCM_CPUS_CFG_PRE_DIV(n) \ 19 __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) 20 #define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) 21 #define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) 22 #define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) 23 #define PRCM_CPUS_CFG_POST_DIV(n) \ 24 __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) 25 #define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) 26 #define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) 27 #define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 28 #define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 29 #define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 30 #define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 31 #define PRCM_CPUS_CFG_CLK_SRC_LOSC \ 32 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) 33 #define PRCM_CPUS_CFG_CLK_SRC_HOSC \ 34 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) 35 #define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ 36 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) 37 #define PRCM_CPUS_CFG_CLK_SRC_PDIV \ 38 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) 39 40 #define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) 41 #define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) 42 #define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) 43 #define PRCM_APB0_RATIO_DIV(n) \ 44 __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) 45 46 #define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) 47 #define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) 48 49 #define PRCM_APB0_GATE_PIO (0x1 << 0) 50 #define PRCM_APB0_GATE_IR (0x1 << 1) 51 #define PRCM_APB0_GATE_TIMER01 (0x1 << 2) 52 #define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ 53 #define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ 54 #define PRCM_APB0_GATE_UART (0x1 << 4) 55 #define PRCM_APB0_GATE_1WIRE (0x1 << 5) 56 #define PRCM_APB0_GATE_I2C (0x1 << 6) 57 58 #define PRCM_APB0_RESET_PIO (0x1 << 0) 59 #define PRCM_APB0_RESET_IR (0x1 << 1) 60 #define PRCM_APB0_RESET_TIMER01 (0x1 << 2) 61 #define PRCM_APB0_RESET_P2WI (0x1 << 3) 62 #define PRCM_APB0_RESET_UART (0x1 << 4) 63 #define PRCM_APB0_RESET_1WIRE (0x1 << 5) 64 #define PRCM_APB0_RESET_I2C (0x1 << 6) 65 66 #define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) 67 #define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) 68 #define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) 69 #define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ 70 __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) 71 #define __PRCM_PLL_CTRL_USB_CLK_0 0x0 72 #define __PRCM_PLL_CTRL_USB_CLK_1 0x1 73 #define __PRCM_PLL_CTRL_USB_CLK_2 0x2 74 #define __PRCM_PLL_CTRL_USB_CLK_3 0x3 75 #define PRCM_PLL_CTRL_USB_CLK_0 \ 76 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) 77 #define PRCM_PLL_CTRL_USB_CLK_1 \ 78 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) 79 #define PRCM_PLL_CTRL_USB_CLK_2 \ 80 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) 81 #define PRCM_PLL_CTRL_USB_CLK_3 \ 82 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) 83 #define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) 84 #define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ 85 __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) 86 #define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ 87 __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) 88 #define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) 89 #define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ 90 __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) 91 #define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 92 #define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 93 #define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 94 #define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 95 #define PRCM_PLL_CTRL_HOSC_CLK_0 \ 96 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) 97 #define PRCM_PLL_CTRL_HOSC_CLK_1 \ 98 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) 99 #define PRCM_PLL_CTRL_HOSC_CLK_2 \ 100 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) 101 #define PRCM_PLL_CTRL_HOSC_CLK_3 \ 102 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) 103 #define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) 104 #define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) 105 #define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) 106 #define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) 107 #define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) 108 #define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ 109 #define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) 110 #define PRCM_PLL_CTRL_LDO_OUT_MASK \ 111 __PRCM_PLL_CTRL_LDO_OUT(0x7) 112 /* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ 113 #define PRCM_PLL_CTRL_LDO_OUT_L(n) \ 114 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) 115 #define PRCM_PLL_CTRL_LDO_OUT_H(n) \ 116 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) 117 #define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ 118 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) 119 #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ 120 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) 121 #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) 122 #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) 123 124 #define PRCM_CLK_1WIRE_GATE (0x1 << 31) 125 126 #define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) 127 #define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) 128 #define __PRCM_CLK_MOD0_M_X(n) (n - 1) 129 #define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) 130 #define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) 131 #define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) 132 #define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) 133 #define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) 134 #define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) 135 #define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) 136 #define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) 137 #define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) 138 #define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) 139 #define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) 140 #define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) 141 142 #define PRCM_APB0_RESET_PIO (0x1 << 0) 143 #define PRCM_APB0_RESET_IR (0x1 << 1) 144 #define PRCM_APB0_RESET_TIMER01 (0x1 << 2) 145 #define PRCM_APB0_RESET_P2WI (0x1 << 3) 146 #define PRCM_APB0_RESET_UART (0x1 << 4) 147 #define PRCM_APB0_RESET_1WIRE (0x1 << 5) 148 #define PRCM_APB0_RESET_I2C (0x1 << 6) 149 150 #define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) 151 #define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) 152 #define __PRCM_CLK_OUTD_M_X() ((n) - 1) 153 #define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) 154 #define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) 155 #define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) 156 #define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) 157 #define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) 158 #define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) 159 #define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) 160 #define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 161 #define __PRCM_CLK_OUTD_SRC_LOSC 0x1 162 #define __PRCM_CLK_OUTD_SRC_HOSC 0x2 163 #define __PRCM_CLK_OUTD_SRC_ERR 0x3 164 #define PRCM_CLK_OUTD_SRC_LOSC2 \ 165 #deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) 166 #define PRCM_CLK_OUTD_SRC_LOSC \ 167 #deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) 168 #define PRCM_CLK_OUTD_SRC_HOSC \ 169 #deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) 170 #define PRCM_CLK_OUTD_SRC_ERR \ 171 #deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) 172 #define PRCM_CLK_OUTD_EN (0x1 << 31) 173 174 #define PRCM_CPU0_PWROFF (0x1 << 0) 175 #define PRCM_CPU1_PWROFF (0x1 << 1) 176 #define PRCM_CPU2_PWROFF (0x1 << 2) 177 #define PRCM_CPU3_PWROFF (0x1 << 3) 178 #define PRCM_CPU_ALL_PWROFF (0xf << 0) 179 180 #define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) 181 #define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) 182 #define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) 183 #define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) 184 185 #define PRCM_VDD_GPU_PWROFF (0x1 << 0) 186 187 #define PRCM_VDD_SYS_RESET (0x1 << 0) 188 189 #define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) 190 #define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) 191 192 #define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) 193 #define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) 194 195 #define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) 196 #define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) 197 198 #define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0) 199 #define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1) 200 #define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2) 201 202 #ifndef __ASSEMBLY__ 203 #include <linux/compiler.h> 204 205 struct __packed sunxi_prcm_reg { 206 u32 cpus_cfg; /* 0x000 */ 207 u8 res0[0x8]; /* 0x004 */ 208 u32 apb0_ratio; /* 0x00c */ 209 u32 cpu0_cfg; /* 0x010 */ 210 u32 cpu1_cfg; /* 0x014 */ 211 u32 cpu2_cfg; /* 0x018 */ 212 u32 cpu3_cfg; /* 0x01c */ 213 u8 res1[0x8]; /* 0x020 */ 214 u32 apb0_gate; /* 0x028 */ 215 u8 res2[0x14]; /* 0x02c */ 216 u32 pll_ctrl0; /* 0x040 */ 217 u32 pll_ctrl1; /* 0x044 */ 218 u8 res3[0x8]; /* 0x048 */ 219 u32 clk_1wire; /* 0x050 */ 220 u32 clk_ir; /* 0x054 */ 221 u8 res4[0x58]; /* 0x058 */ 222 u32 apb0_reset; /* 0x0b0 */ 223 u8 res5[0x3c]; /* 0x0b4 */ 224 u32 clk_outd; /* 0x0f0 */ 225 u8 res6[0xc]; /* 0x0f4 */ 226 u32 cpu_pwroff; /* 0x100 */ 227 u8 res7[0xc]; /* 0x104 */ 228 u32 vdd_sys_pwroff; /* 0x110 */ 229 u8 res8[0x4]; /* 0x114 */ 230 u32 gpu_pwroff; /* 0x118 */ 231 u8 res9[0x4]; /* 0x11c */ 232 u32 vdd_pwr_reset; /* 0x120 */ 233 u8 res10[0x1c]; /* 0x124 */ 234 u32 cpu_pwr_clamp[4]; /* 0x140 but first one is actually unused */ 235 u8 res11[0x30]; /* 0x150 */ 236 u32 dram_pwr; /* 0x180 */ 237 u8 res12[0xc]; /* 0x184 */ 238 u32 dram_tst; /* 0x190 */ 239 u8 res13[0x3c]; /* 0x194 */ 240 u32 prcm_sec_switch; /* 0x1d0 */ 241 }; 242 243 void prcm_apb0_enable(u32 flags); 244 void prcm_apb0_disable(u32 flags); 245 246 #endif /* __ASSEMBLY__ */ 247 #endif /* _PRCM_H */ 248