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Searched refs:PUP_DQS_RD (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_pbs.c701 (PUP_DQS_RD, CS0, in ddr3_pbs_rx()
748 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_pbs_rx()
886 ddr3_write_pup_reg(PUP_DQS_RD, CS0, PUP_BC, 0, INIT_RL_DELAY); in ddr3_pbs_rx()
958 ddr3_write_pup_reg(PUP_DQS_RD, CS0, pup + ecc * ECC_PUP, 0, in ddr3_rx_shift_dqs_to_first_fail()
983 ddr3_write_pup_reg(PUP_DQS_RD, CS0, pup + ecc * ECC_PUP, in ddr3_rx_shift_dqs_to_first_fail()
1046 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_rx_shift_dqs_to_first_fail()
1072 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_rx_shift_dqs_to_first_fail()
Dddr3_dqs.c318 adll_addr = ((is_tx == 1) ? PUP_DQS_WR : PUP_DQS_RD); in ddr3_find_adll_limits()
986 ddr3_write_pup_reg(PUP_DQS_RD, cs, in ddr3_special_pattern_i_search()
1087 ddr3_write_pup_reg(PUP_DQS_RD, in ddr3_special_pattern_i_search()
1146 ddr3_write_pup_reg(PUP_DQS_RD, cs, in ddr3_special_pattern_ii_search()
1238 ddr3_write_pup_reg(PUP_DQS_RD, in ddr3_special_pattern_ii_search()
1316 ddr3_write_pup_reg(PUP_DQS_RD, cs, pup_num, 0, in ddr3_set_dqs_centralization_results()
Dddr3_hw_training.h153 #define PUP_DQS_RD 0x3 macro
Dddr3_hw_training.c706 mode_config[DQS_RD_MODE] = PUP_DQS_RD; in ddr3_save_training()