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Searched refs:PUP_WL_MODE (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_write_leveling.c115 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
126 ddr3_read_pup_reg(PUP_WL_MODE + 0x1, in ddr3_write_leveling_hw()
358 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
389 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
436 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
538 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
551 ddr3_write_pup_reg(PUP_WL_MODE, in ddr3_write_leveling_hw_reg_dimm()
562 ddr3_read_pup_reg(PUP_WL_MODE + 0x1, in ddr3_write_leveling_hw_reg_dimm()
626 ddr3_write_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
1184 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, 0, 0); in ddr3_write_leveling_single_cs()
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Dddr3_hw_training.c559 if (mode == PUP_WL_MODE) in ddr3_write_pup_reg()
704 mode_config[WL_MODE_] = PUP_WL_MODE; in ddr3_save_training()
827 if (reg == PUP_WL_MODE) { in ddr3_read_training_results()
Dddr3_hw_training.h148 #define PUP_WL_MODE 0 macro
Dddr3_pbs.c1511 reg = (ddr3_read_pup_reg(PUP_WL_MODE, cs, pup) & 0x3FF); in ddr3_pbs_write_pup_dqs_reg()
1516 reg |= ((0x4 * cs + PUP_WL_MODE) << REG_PHY_CS_OFFS); in ddr3_pbs_write_pup_dqs_reg()