Searched refs:PhiReg (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 1599 unsigned PhiReg = Phi->getOperand(i).getReg(); in fixupInductionVariable() local
1600 MachineInstr *DI = MRI->getVRegDef(PhiReg); in fixupInductionVariable()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 1640 unsigned PhiReg = Phi->getOperand(i).getReg(); in fixupInductionVariable() local
1641 MachineInstr *DI = MRI->getVRegDef(PhiReg); in fixupInductionVariable()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 2820 unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
2832 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg) in emitLoadM0FromVGPRLoop()
2913 unsigned PhiReg, in loadM0FromVGPR() argument
2954 InitResultReg, DstReg, PhiReg, TmpExec, in loadM0FromVGPR()
3085 unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
3090 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, in emitIndirectSrc()
3200 unsigned PhiReg = MRI.createVirtualRegister(VecRC); in emitIndirectDst() local
3202 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, in emitIndirectDst()
3208 .addReg(PhiReg, RegState::Undef, SubReg) // vdst in emitIndirectDst()
3211 .addReg(PhiReg, RegState::Implicit) in emitIndirectDst()
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