Searched refs:PredOp (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXISelDAGToDAG.cpp | 95 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::Normal, MVT::i32); in SelectBRCOND() local
102 SDValue Ops[] = { Target, Pred, PredOp, Chain }; in SelectBRCOND()
134 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::None, MVT::i32); in SelectREADPARAM() local
137 SDValue Ops[] = { Index, Pred, PredOp, Chain }; in SelectREADPARAM()
172 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::None, MVT::i32); in SelectWRITEPARAM() local
175 SDValue Ops[] = { Value, Pred, PredOp, Chain }; in SelectWRITEPARAM()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| D | PTXInstPrinter.cpp | 71 int PredOp = MI->getOperand(OpIndex).getImm(); in printPredicate() local
72 if (PredOp == PTXPredicate::None) in printPredicate()
75 if (PredOp == PTXPredicate::Negate) in printPredicate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 215 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
226 const MachineOperand &PredOp, bool Cond,
625 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
639 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
857 const MachineOperand &PredOp, bool Cond, in predicateAt() argument
886 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, in predicateAt()
887 PredOp.getSubReg()); in predicateAt()
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| D | HexagonGenMux.cpp | 246 MachineOperand &PredOp = MI->getOperand(1); in genMuxInBlock() local
247 if (PredOp.isUndef()) in genMuxInBlock()
250 unsigned PR = PredOp.getReg(); in genMuxInBlock()
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| D | HexagonISelLowering.cpp | 868 SDValue PredOp = Op.getOperand(0); in LowerVSELECT() local
876 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2); in LowerVSELECT()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 251 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
263 const MachineOperand &PredOp, bool Cond,
613 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
629 .addOperand(PredOp) in genCondTfrFor()
857 const MachineOperand &PredOp, bool Cond, in predicateAt() argument
886 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, in predicateAt()
887 PredOp.getSubReg()); in predicateAt()
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| D | HexagonISelLowering.cpp | 1303 SDValue PredOp = Op.getOperand(0); in LowerVSELECT() local
1311 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2); in LowerVSELECT()
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