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Searched refs:Q24 (Results 1 – 15 of 15) sorted by relevance

/external/libxaac/decoder/
Dixheaacd_constants.h44 #define Q24 16777216 macro
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp141 case AArch64::Q24: in isOdd()
DAArch64RegisterInfo.td398 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
757 def Z24 : AArch64Reg<24, "z24", [Q24, Z24_HI]>, DwarfRegNum<[120]>;
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp141 case AArch64::Q24: in isOdd()
DAArch64RegisterInfo.td379 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1251 case AArch64::Q23: Reg = AArch64::Q24; break; in getNextVectorRegister()
1252 case AArch64::Q24: Reg = AArch64::Q25; break; in getNextVectorRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1139 case AArch64::Q23: Reg = AArch64::Q24; break; in getNextVectorRegister()
1140 case AArch64::Q24: Reg = AArch64::Q25; break; in getNextVectorRegister()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
440 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp301 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
625 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc165 Q24 = 145,
2593 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
3844 { AArch64::Q24, 88U },
4123 { AArch64::Q24, 88U },
19336 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
19338 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
19356 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
19358 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
19360 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
DAArch64GenAsmMatcher.inc10857 case AArch64::Q24: OpKind = MCK_FPR128; break;
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1881 .Case("v24", AArch64::Q24) in matchVectorRegName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp2076 .Case("v24", AArch64::Q24) in MatchNeonVectorRegName()
/external/honggfuzz/examples/apache-httpd/corpus_http1/
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D67154715f57204df236d04030732b84d.000eb1d3.honggfuzz.cov4334 ��@w�w@X!`��� 2�����:T_fU*Ϲ�;�*� 5�D�Q24��L��ޣ.�&IE��������aFi4j[��d�IQ]+���L�B�;y��+$�@…