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/external/libxaac/decoder/armv7/
Dixheaacd_post_twiddle.s136 VMULL.U16 Q8, D4, D8
148 VSHR.U32 Q8, Q8, #16
154 VMLAL.S16 Q8, D5, D8
163 VADD.I32 Q11, Q11, Q8
175 VMOV Q8, Q10
205 VNEG.S32 Q8, Q3
210 VADD.I32 Q8, Q11, Q8
221 VST2.32 {Q7, Q8}, [R0]!
243 VMULL.U16 Q8, D4, D8
256 VSHR.U32 Q8, Q8, #16
[all …]
Dixheaacd_pre_twiddle_compute.s146 VMULL.U16 Q8, D6, D10
151 VSHR.U32 Q8, Q8, #16
162 VMLAL.S16 Q8, D7, D10
170 VSUB.I32 Q11, Q8, Q11
183 VSHL.S32 Q8, Q14, Q7
191 VST2.32 {Q8, Q9}, [R2]!
218 VMULL.U16 Q8, D6, D10
226 VSHR.U32 Q8, Q8, #16
231 VMLAL.S16 Q8, D7, D10
239 VSUB.I32 Q11, Q8, Q11
[all …]
Dixheaacd_overlap_add1.s107 VQADD.S32 Q8, Q8, Q10
110 VQSUB.S32 Q9, Q12, Q8
145 VMULL.S32 Q8, D4, D14
146 VQMOVN.S64 D28, Q8
147 VMULL.S32 Q8, D5, D15
148 VQMOVN.S64 D29, Q8
165 VQADD.S32 Q8, Q8, Q10
169 VQSUB.S32 Q9, Q12, Q8
195 VMULL.S32 Q8, D4, D14
196 VQMOVN.S64 D28, Q8
[all …]
Dixheaacd_overlap_add2.s105 VQADD.S32 Q8, Q9, Q10
108 VQSHL.S32 Q8, Q8, Q11
135 VQADD.S32 Q8, Q9, Q10
136 VQSHL.S32 Q8, Q8, Q11
235 VQADD.S32 Q8, Q9, Q10
238 VQSHL.S32 Q8, Q8, Q11
259 VQADD.S32 Q8, Q9, Q10
260 VQSHL.S32 Q8, Q8, Q11
Dixheaacd_esbr_cos_sin_mod_loop2.s77 VQSUB.S64 Q8, Q2, Q5
81 VSHRN.I64 D16, Q8, #32
108 VQSUB.S64 Q8, Q5, Q2
112 VSHRN.I64 D16, Q8, #32
137 VQSUB.S64 Q8, Q3, Q4
141 VSHRN.I64 D16, Q8, #32
Dixheaacd_dec_DCT2_64_asm.s102 VADD.I32 Q8, Q0, Q2
126 VADD.I32 Q13, Q8, Q15
135 VSUB.I32 Q6, Q8, Q15
149 VADD.I32 Q8, Q0, Q2
181 VADD.I32 Q13, Q8, Q15
186 VSUB.I32 Q6, Q8, Q15
194 VADD.I32 Q8, Q0, Q2
228 VADD.I32 Q13, Q8, Q15
239 VSUB.I32 Q6, Q8, Q15
255 VADD.I32 Q8, Q0, Q2
[all …]
Dixheaacd_post_twiddle_overlap.s48 VDUP.32 Q8, R5
359 VQSHL.S32 Q2, Q2, Q8
360 VQSHL.S32 Q3, Q3, Q8
420 VQSHL.S32 Q4, Q4, Q8
423 VQSHL.S32 Q15, Q15, Q8
615 VQSHL.S32 Q2, Q2, Q8
616 VQSHL.S32 Q3, Q3, Q8
683 VQSHL.S32 Q4, Q4, Q8
686 VQSHL.S32 Q15, Q15, Q8
889 VQSHL.S32 Q2, Q2, Q8
[all …]
Dixheaacd_calc_pre_twid.s51 VMULL.S32 Q8, D0, D8
61 VSHRN.S64 D16, Q8, #32
Dixheaacd_calc_post_twid.s47 VMULL.S32 Q8, D5, D1
56 VSHRN.S64 D7, Q8, #32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfp16-intrinsic-vector-1op.ll14 ; CHECK-HARD-BE: vrev64.16 [[Q8:q[0-9]+]], q0
15 ; CHECK-HARD-BE-NEXT: vabs.f16 [[Q8]], [[Q8]]
16 ; CHECK-HARD-BE-NEXT: vrev64.16 q0, [[Q8]]
28 ; CHECK-SOFTFP-BE: vrev64.16 [[Q8:q[0-9]+]], [[Q8]]
29 ; CHECK-SOFTFP-BE: vabs.f16 [[Q8]], [[Q8]]
30 ; CHECK-SOFTFP-BE: vrev64.16 [[Q8]], [[Q8]]
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s220 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
229 VQMOVUN.S16 D16,Q8
234 VZIP.16 Q7,Q8
247 VZIP.32 Q8,Q11
261 VADDW.U8 Q8,Q5,D28 @//Q2 - HAS Y + R
280 VQMOVUN.S16 D16,Q8
285 VZIP.16 Q7,Q8
298 VZIP.32 Q8,Q11
351 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
360 VQMOVUN.S16 D16,Q8
[all …]
/external/libhevc/common/arm/
Dihevc_resi_trans_32x32_a9q.s169 VSUBL.U8 Q8,D0,D4 @ Get residue 1-8 row 1 -- dual issued with prev. instr. 2nd cycle
210 VADD.S16 Q4, Q8,Q11 @ e[k] = resi_tmp_1 + resi_tmp_2 k -> 1-8 row 1 -- dual issue
212 VSUB.S16 Q6, Q8,Q11 @ o[k] = resi_tmp_1 - resi_tmp_2 k -> 1-8 row 1 -- dual issue
218 VADD.S16 Q8, Q12,Q3 @ e[k] = resi_tmp_1 + resi_tmp_2 k -> 1-8 row 2
229 VADD.S16 Q2, Q8, Q9 @ ee[k] = e[k] + e[16-k] k->1-8 row 2 -- dual issue
230 VSUB.S16 Q3, Q8, Q9 @ eo[k] = e[k] - e[16-k] k->1-8 row 2
279 …VMULL.S16 Q8,D8,D4 @ g_ai2_ihevc_trans_32 * R1eeee[0] R1eeeo[0] R1eeee[0] R1eeeo[0]…
280 … VMLAL.S16 Q8,D10,D5 @ + g_ai2_ihevc_trans_32 * R1eeee[1] R1eeeo[1] R1eeee[1] R1eeeo[1]
288 VZIP.S32 Q8,Q9 @ 3-cycle instruction -- 1st cycle dual issued
298 VMULL.S16 Q8,D26,D1 @g_ai2_ihevc_trans_32[20][0-4] * eeo[0-4] R2
[all …]
Dihevc_sao_edge_offset_class1.s147 VSUB.U8 Q8,Q7,Q6 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
168 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
174 VNEG.S8 Q8,Q10 @sign_up = vnegq_s8(sign_down)
180 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
183 VNEG.S8 Q8,Q4 @II sign_up = vnegq_s8(sign_down)
241 VADD.I8 Q11,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
289 VSUB.U8 Q8,Q7,Q6 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
310 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
316 VNEG.S8 Q8,Q10 @sign_up = vnegq_s8(sign_down)
320 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
[all …]
Dihevc_sao_edge_offset_class1_chroma.s151 VSUB.U8 Q8,Q7,Q6 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
172 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
178 VNEG.S8 Q8,Q10 @sign_up = vnegq_s8(sign_down)
184 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
188 VNEG.S8 Q8,Q14 @II sign_up = vnegq_s8(sign_down)
253 VADD.I8 Q11,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
306 VSUB.U8 Q8,Q7,Q6 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
327 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
333 VNEG.S8 Q8,Q10 @sign_up = vnegq_s8(sign_down)
339 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
[all …]
Dihevc_sao_edge_offset_class0.s167 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
175 … VSUB.I8 Q10,Q9,Q8 @sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
195 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
202 …VSUB.I8 Q11,Q9,Q8 @sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
307 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
309 … VSUB.I8 Q10,Q9,Q8 @sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
315 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
317 …VSUB.I8 Q11,Q9,Q8 @sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
Dihevc_resi_trans.s1028 VADD.S16 Q8 ,Q4,Q5 @e[k] = resi_tmp_1 + resi_tmp_2 k -> 1-8 row 1
1038 @Q8 A1 A2 A3 A4 B1 B2 B3 B4
1041 VADD.S16 Q13,Q8,Q12 @ee[k] = e[k] + e[7 - k] row 1 & 2
1042 VSUB.S16 Q0,Q8,Q12 @eo[k] = e[k] - e[7 - k] row 1 & 2
1106 VMULL.S16 Q8,D27,D1 @g_ai2_ihevc_trans_16[14][0-4] * eo[0-4] R2
1127 VTRN.32 Q6,Q8 @R2 transpose1 -- 2 cycles
1139 VADD.S32 Q6,Q6,Q8 @R2 add
1171 VMULL.S16 Q8,D18,D4 @o[1][0-3]* R1
1174 VMLAL.S16 Q8,D19,D5 @o[1][4-7]* R1
1200 VTRN.32 Q6, Q8 @ 2-cycle instruction
[all …]
Dihevc_sao_edge_offset_class3.s282 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
285 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
301 …VEXT.8 Q9,Q9,Q8,#15 @I pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_…
341 VMOV Q6,Q8
379 …VEXT.8 Q9,Q9,Q8,#15 @II pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next…
419 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
423 VCLT.U8 Q9,Q8,Q9 @III vcltq_u8(pu1_cur_row, pu1_next_row_tmp)
504 …VEXT.8 Q9,Q9,Q8,#15 @pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_ro…
611 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
612 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
[all …]
Dihevc_sao_edge_offset_class2.s261 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
265 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
286 …VEXT.8 Q9,Q8,Q9,#1 @I pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_…
326 VMOV Q6,Q8 @I pu1_cur_row = pu1_next_row
358 …VEXT.8 Q11,Q8,Q14,#1 @II pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row…
384 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
390 VCLT.U8 Q9,Q8,Q9 @III vcltq_u8(pu1_cur_row, pu1_next_row_tmp)
467 …VEXT.8 Q9,Q8,Q9,#1 @pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tm…
573 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
577 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
[all …]
Dihevc_sao_edge_offset_class0_chroma.s174 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
181 … VSUB.U8 Q10,Q9,Q8 @sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
202 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
208 …VSUB.U8 Q11,Q9,Q8 @sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
337 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
344 … VSUB.U8 Q10,Q9,Q8 @sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
362 VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
369 …VSUB.U8 Q11,Q9,Q8 @sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
Dihevc_sao_edge_offset_class3_chroma.s344 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
348 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
375 …VEXT.8 Q9,Q9,Q8,#14 @I pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_…
431 VMOV Q6,Q8 @I pu1_cur_row = pu1_next_row
470 …VEXT.8 Q14,Q14,Q8,#14 @II pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next…
527 VCGT.U8 Q11,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
535 VCLT.U8 Q10,Q8,Q9 @III vcltq_u8(pu1_cur_row, pu1_next_row_tmp)
625 …VEXT.8 Q9,Q9,Q8,#14 @pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_ro…
736 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
740 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
[all …]
Dihevc_sao_edge_offset_class2_chroma.s354 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
366 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
382 …VEXT.8 Q9,Q8,Q9,#2 @I pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_…
436 VMOV Q6,Q8 @I pu1_cur_row = pu1_next_row
470 …VEXT.8 Q14,Q8,Q14,#2 @II pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row…
537 VCGT.U8 Q10,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
539 VCLT.U8 Q11,Q8,Q9 @III vcltq_u8(pu1_cur_row, pu1_next_row_tmp)
616 …VEXT.8 Q9,Q8,Q9,#2 @pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tm…
743 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
744 VSUB.U8 Q7,Q8,Q7 @sign_up = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
[all …]
/external/libavc/common/arm/
Dih264_deblk_luma_a9.s115 vdup.8 q8, r3 @Q8 contains beta
140 vrhadd.u8 q8, q3, q0 @Q8 = ((p0+q0+1) >> 1)
153 vshll.u8 q8, d8, #1 @Q13,Q8 = (p1<<1)
158 vshll.u8 q13, d3, #1 @Q13,Q8 = (q1<<1)
169 vqadd.u8 q8, q3, q9 @Q8 = p0 + delta
176 vbif q8, q3, q12 @Q8 = (i_macro >= 0 ) ? (p0+delta) : (p0-delta)
/external/libxaac/decoder/
Dixheaacd_constants.h34 #define Q8 256 macro
/external/ImageMagick/
DQuickStart.txt112 ftp://ftp.imagemagick.org/pub/ImageMagick/binaries/ImageMagick-7.0.2-0-Q8-windows-dll.exe
113 ftp://ftp.imagemagick.org/pub/ImageMagick/binaries/ImageMagick-7.0.2-0-Q8-windows-static.exe
/external/honggfuzz/examples/apache-httpd/corpus_http2/
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