Searched refs:QCA953X_PLL_DDR_CONFIG_REG (Results 1 – 3 of 3) sorted by relevance
145 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)158 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)161 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
64 val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG); in get_clocks()
420 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 macro