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Searched refs:QPU_W_TMU0_S (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu_validate.c216 (writes_reg(inst, QPU_W_TMU0_S) || in vc4_qpu_validate()
459 if (waddr_add == QPU_W_TMU0_S || in vc4_qpu_validate()
461 waddr_mul == QPU_W_TMU0_S || in vc4_qpu_validate()
Dvc4_qpu_defines.h110 QPU_W_TMU0_S, enumerator
Dvc4_qpu.c275 QPU_W_TMU0_S, in qpu_num_sf_accesses()
336 case QPU_W_TMU0_S: in qpu_waddr_ignores_ws()
Dvc4_qpu_disasm.c186 [QPU_W_TMU0_S] = "tmu0_s",
Dvc4_qpu_schedule.c215 case QPU_W_TMU0_S: in is_tmu_write()
755 if (waddr == QPU_W_TMU0_S) { in waddr_latency()
Dvc4_qpu_emit.c395 dst = qpu_rb(QPU_W_TMU0_S); in vc4_generate_code_block()
/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_validate_shaders.c139 return (waddr == QPU_W_TMU0_S || in is_tmu_submit()
146 return (waddr >= QPU_W_TMU0_S && in is_tmu_write()
427 case QPU_W_TMU0_S: in check_reg_write()
/external/libdrm/vc4/
Dvc4_qpu_defines.h107 QPU_W_TMU0_S, enumerator