| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_apply_rot.s | 30 ADD R11, R0, R5
32 LDRSH R5, [R11, #-98]
33 LDRSH R6, [R11, #94]
34 LDRSH R7, [R11, #-96]
35 LDRSH R8, [R11, #96]
37 STRH R9, [R11, #-98]
39 STRH R10, [R11, #-96]
42 LDRSH R5, [R11, #-2]
43 LDRSH R6, [R11, #190]
44 LDRSH R7, [R11]
[all …]
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| D | ixheaacd_rescale_subbandsamples.s | 26 STMFD SP!, {R4-R11, R14}
59 LDR R11, [R10]
63 MOV R11, R11, LSL R4
64 STR R11, [R10], #4
84 LDR R11, [R10]
88 MOV R11, R11, ASR R4
89 STR R11, [R10], #4
117 LDR R11, [R10]
119 MOV R11, R11, LSL R4
121 STR R11, [R10], #4
[all …]
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| D | ixheaacd_conv_ergtoamplitude.s | 45 MOV R11, R6, LSL R8
47 MOV R11, R11, ASR #5
48 ANDS R11, R11, R14
50 BIC R11, R11, #1
51 LDRH R12, [R11, R5]
73 MOV R11, R6, LSL R8
74 MOV R11, R11, ASR #5
75 ANDS R11, R11, R14
77 BIC R11, R11, #1
78 LDRH R8, [R11, R5]
[all …]
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| D | ixheaacd_enery_calc_per_subband.s | 77 MOVS R11, R2
87 SUBS R11, R11, #2
97 MOV R11, R2
103 SUBS R11, R11, #2
118 SUBS R11, R11, #2
136 SMULBB R11, R4, R9
139 MOV R11, R11, ASR #15
140 CMP R11, #0x00008000
141 MVNEQ R11, R11
142 STRH R11, [R7], #2
[all …]
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| D | ixheaacd_overlap_add2.s | 50 MOV R11, R6, LSL #2
89 VST1.32 {D24[0]}, [R2], R11
91 VST1.32 {D24[1]}, [R2], R11
93 VST1.32 {D25[0]}, [R2], R11
96 VST1.32 {D25[1]}, [R2], R11
109 VST1.32 D16[0], [R2], R11
115 VST1.32 D16[1], [R2], R11
116 VST1.32 D17[0], [R2], R11
117 VST1.32 D17[1], [R2], R11
123 VST1.32 D24[0], [R2], R11
[all …]
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| D | ixheaacd_overlap_add1.s | 36 SUB R11, R10, #1
37 MOV R10, R11, LSL #2
40 MOV R8, R11, LSL #1
54 SUB R11, R5, #1
56 SMULBB R11, R11, R6
57 MOV R11, R11, LSL #1
59 ADD R11, R11, R2
124 VST1.16 D26[0], [R11], R4
126 VST1.16 D26[1], [R11], R4
128 VST1.16 D26[2], [R11], R4
[all …]
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| D | ixheaacd_cos_sin_mod.s | 72 ADD R11, R10, R6
137 STR R12, [R11, #-4]
138 STR R3, [R11], #-8
153 STR R3, [R11, #0x108]
154 STR R14, [R11, #0x104]
196 STR R3, [R11], #-4
197 STR R12, [R11], #-4
213 STR R3, [R11, #0x104]
214 STR R12, [R11, #0x108]
279 LDR R11, [R8, #4]
[all …]
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| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 34 ADD R11, R10, R2, LSL #3
35 SUB R11, R11, #4
55 VLD1.32 {D2[1]}, [R11] @re = *psubband12;
62 STR R7, [R11], #-4
68 VLD1.32 {D3[1]}, [R11]
92 VST1.32 {D16[1]}, [R11], R8
98 LDR R6, [R11] @RE3
118 VST1.32 {D12[1]}, [R11], R8
128 VLD1.32 {D2[1]}, [R11]
150 VST1.32 {D16[1]}, [R11], R8
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| D | ixheaacd_post_twiddle_overlap.s | 64 SMULWT R11, R8, R10
68 SUB R8, R12, R11
75 SMULWB R11, R8, R12
78 ADD R5, R5, R11
80 LDR R11, [sp, #104]
89 CMP R11, #0
92 RSBS R9, R11, #16
101 RSBS R9, R11, #31
106 MOVEQ R7, R7, LSL R11
108 RSBS R9, R11, #31
[all …]
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| D | ixheaacd_sbr_qmfsyn64_winadd.s | 42 MOV R11, R2
85 MOV R2, R11
95 MOV R11, R12
119 MOV R12, R11
129 MOV R11, R2
155 MOV R2, R11
163 MOV R11, R12
181 MOV R12, R11
206 MOV R11, R2
242 MOV R2, R11
[all …]
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| D | ixheaacd_tns_parcor2lpc_32x16.s | 48 MOV R11, R10
98 QADD R11, R11, R5
100 MOV R11, R11, ASR #16
102 STRH R11, [R4]
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| D | ixheaacd_esbr_qmfsyn64_winadd.s | 31 MOV R11, R2
81 MOV R2, R11
86 MOV R11, R12
130 MOV R12, R11
137 MOV R11, R2
174 MOV R2, R11
179 MOV R11, R12
220 MOV R12, R11
232 MOV R11, R2
263 MOV R2, R11
[all …]
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| D | ixheaacd_tns_ar_filter_fixed.s | 152 @VMOV R11,D6[0]
154 LDR R11, [SP]
192 @VMOV R11,D6[0]
194 LDR R11, [SP]
237 @VMOV R11,D6[0]
239 LDR R11, [SP]
284 @VMOV R11,D6[0]
286 LDR R11, [SP]
334 @VMOV R11,D6[0]
336 LDR R11, [SP]
[all …]
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| D | ixheaacd_dct3_32.s | 44 MOV R11, #-4
133 VLD1.32 {Q1}, [R7], R11
149 VLD1.32 {Q4}, [R5], R11
181 VLD1.32 D2[0], [R7], R11
184 VLD1.32 D2[1], [R7], R11
188 VLD1.32 D3[0], [R7], R11
198 VLD1.32 D8[0], [R5], R11
205 VLD1.32 D8[1], [R5], R11
210 VLD1.32 D9[0], [R5], R11
230 VLD1.32 D2[0], [R7], R11
[all …]
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| D | ixheaacd_conv_ergtoamplitudelp.s | 31 MOVW R11, #0x5A82
55 SMULWBNE R12, R12, R11
81 SMULWBNE R8, R8, R11
109 SMULWBNE R8, R8, R11
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| D | ixheaacd_sbr_qmfanal32_winadds.s | 80 MOV R11, R4
82 ADD R11, R11, #128
186 VST1.32 {Q15}, [R11]!
261 VST1.32 {Q15}, [R11]!
|
| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | sum_arm.s | 34 MOVW R4>>14, R11
38 ORR R5<<18, R11, R11
43 AND R11, R5, R5
110 MOVW R1>>20, R11
115 ORR R2<<12, R11, R11
120 BIC $0xfc000000, R11, R11
125 ADD R11, R7, R7
130 MULLU R4, R5, (R11, g)
132 MULALU R3, R6, (R11, g)
134 MULALU R2, R7, (R11, g)
[all …]
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| /external/boringssl/src/ssl/test/runner/curve25519/ |
| D | ladderstep_amd64.s | 23 MOVQ CX,R11
28 ADDQ ·_2P1234(SB),R11
38 SUBQ 96(DI),R11
48 MOVQ R11,56(SP)
64 MOVQ DX,R11
78 ADCQ DX,R11
117 ADCQ DX,R11
129 SHLQ $13,R11:R10
134 ADDQ R11,R12
179 MOVQ DX,R11
[all …]
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| D | freeze_amd64.s | 24 MOVQ $3,R11
47 SUBQ $1,R11
51 CMOVQLT R11,R12
53 CMOVQNE R11,R12
55 CMOVQNE R11,R12
57 CMOVQNE R11,R12
59 CMOVQNE R11,R12
|
| D | square_amd64.s | 29 MOVQ AX,R11
43 ADDQ AX,R11
82 ADDQ AX,R11
95 SHLQ $13,R12:R11
96 ANDQ SI,R11
97 ADDQ R10,R11
112 ADDQ R11,DX
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| D | mul_amd64.s | 38 MOVQ DX,R11
54 ADCQ DX,R11
93 ADCQ DX,R11
105 ADCQ DX,R11
117 ADCQ DX,R11
129 SHLQ $13,R11:R10
134 ADDQ R11,R12
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 153 @R11 tmp register
240 ADD R11,R9,R12,LSL #2 @Load address of g_ai2_ihevc_trans_32[4]
244 VLD1.S16 D24,[R11],R12 @ LOAD g_ai2_ihevc_trans_32[4][0-4]
281 …VLD1.S16 D27,[R11],R12 @LOAD g_ai2_ihevc_trans_32[12][0-4] -- 1st cycle dual issue with p…
296 VLD1.S16 D26,[R11],R12 @LOAD g_ai2_ihevc_trans_32[20][0-4]
306 VLD1.S16 D27,[R11],R12 @LOAD g_ai2_ihevc_trans_32[28][0-4]
320 ADD R11,R9,R12,LSL #1 @Load address of g_ai2_ihevc_trans_32[2]
322 VLD1.S16 {D0,D1},[R11],R12 @g_ai2_ihevc_trans_32[2][0-7]
344 VLD1.S16 {D0,D1},[R11],R12 @g_ai2_ihevc_trans_32[6][0-7]
354 VLD1.S16 {D0,D1},[R11],R12 @g_ai2_ihevc_trans_32[10][0-7] -- dual issue with prev. MLAL
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | ShadowCallStack.cpp | 92 const MCPhysReg OffsetReg = X86::R11; in addProlog()
132 .addDef(X86::R11) in addEpilog()
133 .addReg(X86::R11, RegState::Undef) in addEpilog()
134 .addReg(X86::R11, RegState::Undef); in addEpilog()
137 X86::GS, X86::R11); in addEpilog()
144 X86::GS, X86::R11) in addEpilog()
204 if (Fn.front().isLiveIn(X86::R10) || Fn.front().isLiveIn(X86::R11)) in runOnMachineFunction()
311 else if (MI.findRegisterUseOperand(X86::R11)) in runOnMachineFunction()
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | atomic.ll | 90 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
91 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
121 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
122 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
153 ; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]]
154 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
212 ; CHECK: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]]
220 ; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.cpp | 44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
|