/external/boringssl/src/crypto/poly1305/ |
D | poly1305_vec.c | 65 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member 114 p->R22.d[1] = (uint32_t)(r2); in CRYPTO_poly1305_init() 115 p->R22.d[3] = (uint32_t)(r2 >> 32); in CRYPTO_poly1305_init() 153 r2 = ((uint64_t)p->R22.d[3] << 32) | (uint64_t)p->R22.d[1]; in poly1305_first_block() 186 p->R22.v = in poly1305_first_block() 195 p->S22.v = _mm_mul_epu32(p->R22.v, FIVE); in poly1305_first_block() 207 p->R22.d[1] = (uint32_t)(r2); in poly1305_first_block() 208 p->R22.d[3] = (uint32_t)(r2 >> 32); in poly1305_first_block() 250 T2 = _mm_mul_epu32(H0, p->R22.v); in poly1305_blocks() 270 T6 = _mm_mul_epu32(H1, p->R22.v); in poly1305_blocks() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 67 def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>; 95 def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>; 117 add R24, R25, R18, R19, R20, R21, R22, R23, 135 add R24, R25, R18, R19, R20, R21, R22, R23, 145 add R23, R22, R21, R20, R19, R18, R17, R16
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D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18. 49 CCIfType<[i8], CCAssignToReg<[R24,R22]>>,
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/external/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 67 def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>; 95 def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>; 119 add R24, R25, R18, R19, R20, R21, R22, R23, 137 add R24, R25, R18, R19, R20, R21, R22, R23, 147 add R23, R22, R21, R20, R19, R18, R17, R16
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D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18. 56 CCIfType<[i8], CCAssignToReg<[R24,R22]>>,
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
D | MBlazeBaseInfo.h | 127 case MBlaze::R22 : return 22; in getMBlazeRegisterNumbering() 192 case 22 : return MBlaze::R22; in getMBlazeRegisterFromNumbering()
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPUCallingConv.td | 27 R21, R22, R23, R24, R25, R26, R27, R28, R29, 44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/ |
D | two-extenders.s | 102 {R22 = #1; memb(##0x1000) = R22.new}
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
D | ARCRegisterInfo.td | 55 def R22 : Core<22, "%r22">, DwarfRegNum<[22]>; 74 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCFrameLowering.h | 163 {PPC::R22, -40}, in getCalleeSavedSpillSlots() 242 {PPC::R22, -76}, in getCalleeSavedSpillSlots()
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/external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/ |
D | ppc_asm.h | 23 #define R22 r22 macro
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/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/ |
D | ppc_asm.h | 18 #define R22 r22 macro
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 108 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs() 117 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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D | HexagonFrameLowering.h | 66 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 }, in getCalleeSavedSpillSlots()
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/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiBaseInfo.h | 94 case Lanai::R22: in getLanaiRegisterNumbering()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiBaseInfo.h | 94 case Lanai::R22: in getLanaiRegisterNumbering()
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaRegisterInfo.td | 60 def R22 : GPR<22, "$22">, DwarfRegNum<[22]>; 115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
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/external/autotest/test_suites/ |
D | control.power_requirements | 17 Ex: x86-mario-release/R22-2494.33.0
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
D | PPCBaseInfo.h | 53 case R22: case X22: case F22: case V22: case CR5EQ: return 22; in getPPCRegisterNumbering()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 106 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs() 115 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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D | HexagonRegisterInfo.td | 109 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 309 (add R23, R22, R21, R20, R19, R18, R17, R16, 393 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
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D | HexagonFrameLowering.h | 89 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 }, in getCalleeSavedSpillSlots()
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeRegisterInfo.cpp | 61 MBlaze::R20, MBlaze::R21, MBlaze::R22, MBlaze::R23, in getCalleeSavedRegs()
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/external/llvm/lib/Target/Lanai/Disassembler/ |
D | LanaiDisassembler.cpp | 159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/Disassembler/ |
D | LanaiDisassembler.cpp | 157 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
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