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/external/swiftshader/third_party/LLVM/test/TableGen/
DTree.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
DTreeNames.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
DTargetInstrInfo.td37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTree.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
DTreeNames.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
DTargetInstrInfo.td37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
/external/llvm/test/TableGen/
DTree.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
DTreeNames.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
DTargetInstrInfo.td37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
/external/python/cpython2/Modules/
Dshamodule.c130 #define R32(x,n) ((x << n) | (x >> (32 - n))) macro
135 T = R32(A,5) + f##n(B,C,D) + E + *WP++ + CONST##n; \
136 E = D; D = C; C = R32(B,30); B = A; A = T
141 T = R32(A,5) + f##n(B,C,D) + E + *WP++ + CONST##n; B = R32(B,30)
144 E = R32(T,5) + f##n(A,B,C) + D + *WP++ + CONST##n; A = R32(A,30)
147 D = R32(E,5) + f##n(T,A,B) + C + *WP++ + CONST##n; T = R32(T,30)
150 C = R32(D,5) + f##n(E,T,A) + B + *WP++ + CONST##n; E = R32(E,30)
153 B = R32(C,5) + f##n(D,E,T) + A + *WP++ + CONST##n; D = R32(D,30)
156 A = R32(B,5) + f##n(C,D,E) + T + *WP++ + CONST##n; C = R32(C,30)
173 W[i] = R32(W[i], 1); in sha_transform()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-legalize-divmod.mir131 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
137 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
139 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
183 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
189 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
191 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
237 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
243 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
245 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
289 ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
[all …]
/external/autotest/server/site_tests/autoupdate_Rollback/
Dcontrol36 gs://chromeos-image-archive/parrot-release/R32-4793.0.0&\
40 parrot-release/R32-4793.0.0/autotest/packages"
45 parrot-release/R32-4793.0.0/autotest/packages" --fast \
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_formats.c174 F3(A, L32_FLOAT, R32_FLOAT, R, R, R, xx, FLOAT, R32, TB),
175 I3(A, L32_SINT, R32_SINT, R, R, R, xx, SINT, R32, TR),
176 I3(A, L32_UINT, R32_UINT, R, R, R, xx, UINT, R32, TR),
187 C4(A, I32_FLOAT, R32_FLOAT, R, R, R, R, FLOAT, R32, TR),
188 C4(A, I32_SINT, R32_SINT, R, R, R, R, SINT, R32, TR),
189 C4(A, I32_UINT, R32_UINT, R, R, R, R, UINT, R32, TR),
200 A1(A, A32_FLOAT, R32_FLOAT, xx, xx, xx, R, FLOAT, R32, T),
201 A1(A, A32_SINT, R32_SINT, xx, xx, xx, R, SINT, R32, T),
202 A1(A, A32_UINT, R32_UINT, xx, xx, xx, R, UINT, R32, T),
305 F1(A, R32_FLOAT, R32_FLOAT, R, xx, xx, xx, FLOAT, R32, IB),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Df16-instructions.ll31 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
32 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
46 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
47 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
61 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000;
62 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
75 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000;
76 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
90 ; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
91 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
[all …]
Dparam-load-store.ll140 ; CHECK: ld.param.b32 [[R32:%r[0-9]+]], [retval0+0];
141 ; CHECK: and.b32 [[R:%r[0-9]+]], [[R32]], 255;
160 ; CHECK: ld.param.b32 [[R32:%r[0-9]+]], [retval0+0];
162 ; CHECK: cvt.u16.u32 [[R16:%rs[0-9]+]], [[R32]];
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td28 R30, R31, R32, R33, R34, R35, R36, R37, R38,
45 R30, R31, R32, R33, R34, R35, R36, R37, R38,
DSPURegisterInfo.cpp86 case SPU::R32: return 32; in getRegisterNumbering()
DSPURegisterInfo.td56 def R32 : SPUVecReg<32, "$32">, DwarfRegNum<[32]>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D2006-05-08-CoalesceSubRegClass.ll1 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
/external/llvm/test/CodeGen/X86/
D2006-05-08-CoalesceSubRegClass.ll1 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2006-05-08-CoalesceSubRegClass.ll1 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Drotate.ll47 ; CHECK: r[[R32:[0-9]+]] = and(r[[R30]],#31)
48 ; CHECK: r[[R33:[0-9]+]] = asl(r0,r[[R32]])
/external/autotest/docs/
Dtest-that.md98 test_that -b peach_pit :lab: suite:pyauto_perf -i 'peach_pit-release/R32-4763.0.0'
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp1383 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass; in generateInserts() local
1384 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert) in generateInserts()
1389 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) { in generateInserts()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp1415 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass; in generateInserts() local
1416 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert) in generateInserts()
1421 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) { in generateInserts()

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