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Searched refs:R600 (Results 1 – 25 of 169) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp67 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
68 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
69 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
70 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
72 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
73 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
74 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
75 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
82 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
89 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
[all …]
DR600RegisterInfo.cpp38 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
39 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
40 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
41 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
42 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::PV_X); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::ALU_CONST); in getReservedRegs()
47 reserveRegisterTuples(Reserved, R600::PREDICATE_BIT); in getReservedRegs()
[all …]
DR600ControlFlowFinalizer.cpp97 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
106 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
107 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
108 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
109 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
171 case R600::CF_PUSH_EG: in pushBranch()
172 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
243 case R600::KILL: in IsTrivialInst()
244 case R600::RETURN: in IsTrivialInst()
256 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600; in getHWInstrDesc()
[all …]
DR600ExpandSpecialInstrs.cpp99 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
103 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
104 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
106 R600::OpName::pred_sel); in runOnMachineFunction()
108 R600::OpName::pred_sel); in runOnMachineFunction()
117 case R600::PRED_X: { in runOnMachineFunction()
125 R600::ZERO); // src1 in runOnMachineFunction()
128 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
130 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
135 case R600::DOT_4: { in runOnMachineFunction()
[all …]
DR600EmitClauseMarkers.cpp55 case R600::INTERP_PAIR_XY: in OccupiedDwords()
56 case R600::INTERP_PAIR_ZW: in OccupiedDwords()
57 case R600::INTERP_VEC_LOAD: in OccupiedDwords()
58 case R600::DOT_4: in OccupiedDwords()
60 case R600::KILL: in OccupiedDwords()
80 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in OccupiedDwords()
92 case R600::PRED_X: in isALU()
93 case R600::INTERP_PAIR_XY: in isALU()
94 case R600::INTERP_PAIR_ZW: in isALU()
95 case R600::INTERP_VEC_LOAD: in isALU()
[all …]
DR600MachineScheduler.cpp165 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in schedNode()
184 if (MI->getOpcode() != R600::COPY) in isPhysicalRegCopy()
227 case R600::PRED_X: in getAluKind()
229 case R600::INTERP_PAIR_XY: in getAluKind()
230 case R600::INTERP_PAIR_ZW: in getAluKind()
231 case R600::INTERP_VEC_LOAD: in getAluKind()
232 case R600::DOT_4: in getAluKind()
234 case R600::COPY: in getAluKind()
250 MI->getOpcode() == R600::GROUP_BARRIER) { in getAluKind()
261 case R600::sub0: in getAluKind()
[all …]
DR600ClauseMergePass.cpp37 case R600::CF_ALU: in isCFAlu()
38 case R600::CF_ALU_PUSH_BEFORE: in isCFAlu()
88 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
95 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
101 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
120 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
128 if (RootCFAlu.getOpcode() == R600::CF_ALU_PUSH_BEFORE) in mergeIfPossible()
132 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
134 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
136 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
[all …]
DR600Packetizer.cpp87 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
90 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
96 Result[Dst] = R600::PS; in getPreviousVector()
99 if (BI->getOpcode() == R600::DOT4_r600 || in getPreviousVector()
100 BI->getOpcode() == R600::DOT4_eg) { in getPreviousVector()
101 Result[Dst] = R600::PV_X; in getPreviousVector()
104 if (Dst == R600::OQAP) { in getPreviousVector()
110 PVReg = R600::PV_X; in getPreviousVector()
113 PVReg = R600::PV_Y; in getPreviousVector()
116 PVReg = R600::PV_Z; in getPreviousVector()
[all …]
DR600ISelLowering.cpp58 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
59 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
60 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
61 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
62 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
63 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
286 return std::next(I)->getOpcode() == R600::RETURN; in isEOP()
302 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
308 MI.getOpcode() == R600::LDS_CMPST_RET) in EmitInstrWithCustomInserter()
312 TII->get(R600::getLDSNoRetOp(MI.getOpcode()))); in EmitInstrWithCustomInserter()
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dfdiv.ll6 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
15 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
16 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
38 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
39 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
54 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
55 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
70 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
71 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
72 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
[all …]
Dsetcc.ll2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
7 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
8 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
18 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38 ; R600: SETE_DX10
49 ; R600: SETGT_DX10
60 ; R600: SETGE_DX10
[all …]
Dfadd.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
[all …]
Dbuild_vector.ll1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
5 ; R600: {{^}}build_vector2:
6 ; R600: MOV
7 ; R600: MOV
8 ; R600-NOT: MOV
19 ; R600: {{^}}build_vector4:
20 ; R600: MOV
21 ; R600: MOV
22 ; R600: MOV
23 ; R600: MOV
[all …]
Duint_to_fp.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
8 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
18 ; R600: INT_TO_FLT
33 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
34 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
48 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
49 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
50 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
51 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
65 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
[all …]
Dload-global-f32.ll5 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
12 ; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
24 ; R600: VTX_READ_64
36 ; R600: VTX_READ_128
48 ; R600: VTX_READ_128
62 ; R600: VTX_READ_128
63 ; R600: VTX_READ_128
82 ; R600: VTX_READ_128
83 ; R600: VTX_READ_128
[all …]
Dfneg.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; R600: -PV
16 ; R600: -PV
17 ; R600: -PV
28 ; R600: -PV
29 ; R600: -T
30 ; R600: -PV
31 ; R600: -PV
48 ; R600-NOT: XOR
49 ; R600: -KC0[2].Z
Dfabs.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
11 ; R600-NOT: AND
12 ; R600: |PV.{{[XYZW]}}|
24 ; R600-NOT: AND
25 ; R600: |PV.{{[XYZW]}}|
37 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
47 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
48 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
59 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
60 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dnullptr.ll2 … -march=r600 -mtriple=r600---amdgiz -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s
12 ; R600-NEXT: .long 0
17 ; R600-NEXT: .long 0
29 ; R600-NEXT: .long 0
33 ; R600-NEXT: .long 0
37 ; R600-NEXT: .long 0
41 ; R600-NEXT: .long 0
45 ; R600-NEXT: .long 0
49 ; R600-NEXT: .long 0
53 ; R600-NEXT: .long 0
[all …]
Dfdiv.ll4 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
13 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
14 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
38 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
39 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
101 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
102 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
116 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
117 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
131 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
[all …]
Dfadd.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
[all …]
Dbuild_vector.ll1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
5 ; R600: {{^}}build_vector2:
6 ; R600: MOV
7 ; R600: MOV
8 ; R600-NOT: MOV
19 ; R600: {{^}}build_vector4:
20 ; R600: MOV
21 ; R600: MOV
22 ; R600: MOV
23 ; R600: MOV
[all …]
Dsetcc.ll2 …achineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC …
7 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
8 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
20 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
22 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
23 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: SETE_DX10
55 ; R600: SETGT_DX10
66 ; R600: SETGE_DX10
[all …]
Duint_to_fp.ll3 …mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC …
8 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
18 ; R600: INT_TO_FLT
33 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
34 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
48 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
49 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
50 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
51 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
65 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
[all …]
Dload-global-f32.ll5 …bal-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC …
6 …obal-loads=false -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC …
12 ; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
24 ; R600: VTX_READ_64
36 ; R600: VTX_READ_128
48 ; R600: VTX_READ_128
62 ; R600: VTX_READ_128
63 ; R600: VTX_READ_128
82 ; R600: VTX_READ_128
83 ; R600: VTX_READ_128
[all …]
Dfneg.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; R600: -PV
16 ; R600: -PV
17 ; R600: -PV
28 ; R600: -PV
29 ; R600: -T
30 ; R600: -PV
31 ; R600: -PV
51 ; R600-NOT: XOR
52 ; R600: -KC0[2].Z
[all …]

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