Home
last modified time | relevance | path

Searched refs:R8 (Results 1 – 25 of 475) sorted by relevance

12345678910>>...19

/external/libxaac/decoder/armv7/
Dixheaacd_conv_ergtoamplitude.s42 CLZ R8, R6
43 SUB R8, R8, #17
44 SUB R7, R7, R8
45 MOV R11, R6, LSL R8
66 MOV R8, #0
70 CLZ R8, R6
71 SUB R8, R8, #17
72 SUB R7, R7, R8
73 MOV R11, R6, LSL R8
78 LDRH R8, [R11, R5]
[all …]
Dixheaacd_conv_ergtoamplitudelp.s43 CLZ R8, R6
44 SUB R8, R8, #17
45 SUB R7, R7, R8
46 MOV R6, R6, LSL R8
62 MOV R8, #0
69 CLZ R8, R6
70 SUB R8, R8, #17
71 SUB R7, R7, R8
72 MOV R6, R6, LSL R8
78 LDRH R8, [R6, R5]
[all …]
Dixheaacd_apply_rot.s35 LDRSH R8, [R11, #96]
38 ADD R10, R7, R8
45 LDRSH R8, [R11, #192]
48 ADD R10, R7, R8
54 LDRSH R8, [R11, #96]
57 ADD R10, R7, R8
65 LDRSH R8, [R11, #192]
68 ADD R10, R7, R8
83 LDR R8, [R11, #92]
86 SMULWB R10, R6, R8
[all …]
Dixheaacd_rescale_subbandsamples.s46 LDR R8, [SP, #48]
47 MOVS R8, R8
111 LDR R8, [R5], #4
113 ADD R8, R8, R2, LSL #2
118 LDR R1, [R8]
122 STR R1, [R8], #4
125 LDR R1, [R8]
129 STR R1, [R8], #4
139 LDR R1, [R8]
143 STR R1, [R8], #4
[all …]
Dixheaacd_cos_sin_mod.s47 MOV R8, R0
71 LDR R0, [R8], #4
98 LDR R0, [R8, #0xFC]
113 LDR R1, [R8], #4
135 LDR R1, [R8, #0xFC]
151 LDR R0, [R8], #4
160 LDR R0, [R8, #0xFC]
175 LDR R1, [R8], #4
195 LDR R1, [R8, #0xFC]
211 LDRGT R0, [R8], #4
[all …]
Dixheaacd_sbr_qmfsyn64_winadd.s58 MOV R8, R7, LSL #1
61 VLD1.16 D2, [R0], R8
68 VLD1.16 D4, [R0], R8
73 VLD1.16 D6, [R0], R8
78 VLD1.16 D8, [R0], R8
96 VLD1.16 D12, [R1], R8
102 VLD1.16 D14, [R1], R8
107 VLD1.16 D16, [R1], R8
112 VLD1.16 D18, [R1], R8
130 VLD1.16 D2, [R0], R8
[all …]
Dixheaacd_esbr_qmfsyn64_winadd.s45 MOV R8, R7, LSL #1 @(512*2)
54 VLD1.32 {D4, D5}, [R0], R8
60 VLD1.32 {D8, D9}, [R0], R8
66 VLD1.32 {D12, D13}, [R0], R8
72 VLD1.32 {D16, D17}, [R0], R8
90 VLD1.32 {D4, D5}, [R1], R8
98 VLD1.32 {D8, D9}, [R1], R8
104 VLD1.32 {D12, D13}, [R1], R8
110 VLD1.32 {D16, D17}, [R1], R8
147 VLD1.32 {D4, D5}, [R0], R8
[all …]
Dixheaacd_overlap_add2.s38 MOV R8, #1
39 MOV R8, R8, LSL R9
42 VDUP.32 Q10, R8
43 MOV R8, R5
74 SUB R8, R8, #8
113 SUBS R8, R8, #8
152 MOV R8, R6, LSL #2
217 VST1.32 D24[0], [R7], R8
219 VST1.32 D24[1], [R7], R8
221 VST1.32 D25[0], [R7], R8
[all …]
Dixheaacd_enery_calc_per_subband.s46 LDR R8, [sp, #0x30]
51 MOVS R8, R8
76 MOV R8, R0
82 LDR R4, [R8], #0x100
83 LDR R12, [R8], #0x100
96 MOV R8, R0
101 LDR R4, [R8], #0x100
102 LDR R12, [R8], #0x100
116 LDR R4, [R8], #0x100
117 LDR R3, [R8], #0x100
Dixheaacd_pre_twiddle_compute.s31 MOVW R8, #7500
32 ADD R3, R3, R8
44 LDR R8, [R3], #4
47 SMULWB R12, R9, R8
49 SMULWT R11, R9, R8
50 SMLAWT R9, R10, R8, R12
51 SMULWB R6, R10, R8
60 MVN R8, R5
61 ADD R8, R8, #1
62 ASR R11, R11, R8
[all …]
Dia_xheaacd_mps_reoder_mulshift_acc.s38 LSL R8, R5, #2
39 SUB R8, R7, R8
44 SUB R8, R8, #32
45 VLD1.32 {Q0, Q1}, [R8]
55 MOV R8, R0
59 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
99 MOV R8, R0
103 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
142 MOV R8, R0
147 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
[all …]
Dixheaacd_post_twiddle.s53 LDR R8, [R1], #4
57 SMULWT R11, R8, R9
58 SMULWB R10, R8, R9
60 SMLAWB R8, R7, R9, R11
64 MVN R8, R8
65 ADD R8, R8, #1
67 SMLAWB R9, R10, R5, R8
68 SMLAWB R11, R8, R4, R10
98 MOV R8, #-32
102 VLD4.16 {D0, D1, D2, D3}, [R5], R8
[all …]
Dixheaacd_calc_post_twid.s35 MOV R8, #8
70 VST1.32 {D0[0]}, [R0], R8
72 VST1.32 {D0[1]}, [R0], R8
75 VST1.32 {D2[0]}, [R0], R8
77 VST1.32 {D2[1]}, [R0], R8
/external/boringssl/src/ssl/test/runner/curve25519/
Dcswap_amd64.s19 MOVQ 88(DI),R8
24 CMOVQEQ R8,CX
25 CMOVQEQ R9,R8
29 MOVQ R8,88(DI)
33 MOVQ 104(DI),R8
38 CMOVQEQ R8,CX
39 CMOVQEQ R9,R8
43 MOVQ R8,104(DI)
47 MOVQ 120(DI),R8
52 CMOVQEQ R8,CX
[all …]
Dladderstep_amd64.s19 MOVQ 64(DI),R8
24 MOVQ R8,R12
34 ADDQ 104(DI),R8
44 MOVQ R8,24(SP)
58 MOVQ AX,R8
106 ADDQ AX,R8
111 ADDQ AX,R8
126 SHLQ $13,R9:R8
127 ANDQ DX,R8
128 ADDQ CX,R8
[all …]
Dmul_amd64.s23 MOVQ AX,R8
29 ADDQ AX,R8
33 ADDQ AX,R8
70 ADDQ AX,R8
87 ADDQ AX,R8
127 SHLQ $13,R9:R8
128 ANDQ SI,R8
142 ADDQ DX,R8
143 MOVQ R8,DX
148 ANDQ SI,R8
[all …]
Dfreeze_amd64.s19 MOVQ 24(DI),R8
37 ADDQ R12,R8
38 MOVQ R8,R12
40 ANDQ AX,R8
56 CMPQ AX,R8
66 SUBQ AX,R8
71 MOVQ R8,24(DI)
Dsquare_amd64.s20 MOVQ DX,R8
59 ADCQ DX,R8
68 ADCQ DX,R8
90 SHLQ $13,R8:CX
94 ADDQ R8,R9
110 MOVQ DX,R8
113 ANDQ SI,R8
128 MOVQ R8,8(DI)
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s139 @LDR R8,[sp,#52]
146 @SUB R12,R8,R3, LSR #1 @// v offset
154 ADD R8,R2,R9,LSL #2 @// rgb_next_row = rgb + rgb_stride
300 VST1.32 D14,[R8]!
301 VST1.32 D15,[R8]!
302 VST1.32 D20,[R8]!
303 VST1.32 D21,[R8]!
304 VST1.32 D16,[R8]!
305 VST1.32 D17,[R8]!
306 VST1.32 D22,[R8]!
[all …]
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_amd64.s72 XORQ R8, R8 // h0
80 POLY1305_ADD(SI, R8, R9, R10)
83 POLY1305_MUL(R8, R9, R10, R11, R12, BX, CX, R13, R14)
105 ADDQ BX, R8
112 MOVQ R8, AX
117 CMOVQCS R8, AX
119 MOVQ key+24(FP), R8
120 ADDQ 16(R8), AX
121 ADCQ 24(R8), BX
Dsum_arm.s27 ADD $4, R13, R8
28 MOVM.IB [R4-R7], (R8)
31 MOVW R2, R8
40 AND R8, R2, R2
76 MOVM.IB [R4-R8, R14], (R12)
82 MOVW 56(R0), R8
127 ADD R12, R8, R8
138 MULALU R1, R8, (R11, g)
139 MULALU R0, R8, (R14, R12)
154 MULALU R4, R8, (R11, g)
[all …]
/external/llvm/test/TableGen/
DTargetInstrInfo.td35 def R8 : RegisterClass;
87 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
89 [(set R8:$dst, R8:$src)]>;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrInfo.td35 def R8 : RegisterClass;
87 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
89 [(set R8:$dst, R8:$src)]>;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td35 def R8 : RegisterClass;
87 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
89 [(set R8:$dst, R8:$src)]>;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.td29 // A SwiftError is passed in R8.
30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
54 // A SwiftError is returned in R8.
55 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
118 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
169 // A SwiftError is passed in R8.
170 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
185 // A SwiftError is returned in R8.
186 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
210 // A SwiftError is passed in R8.
[all …]

12345678910>>...19