1 /* 2 * r8a7793 clock definition 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ 17 #define __DT_BINDINGS_CLOCK_R8A7793_H__ 18 19 /* CPG */ 20 #define R8A7793_CLK_MAIN 0 21 #define R8A7793_CLK_PLL0 1 22 #define R8A7793_CLK_PLL1 2 23 #define R8A7793_CLK_PLL3 3 24 #define R8A7793_CLK_LB 4 25 #define R8A7793_CLK_QSPI 5 26 #define R8A7793_CLK_SDH 6 27 #define R8A7793_CLK_SD0 7 28 #define R8A7793_CLK_Z 8 29 #define R8A7793_CLK_RCAN 9 30 #define R8A7793_CLK_ADSP 10 31 32 /* MSTP0 */ 33 #define R8A7793_CLK_MSIOF0 0 34 35 /* MSTP1 */ 36 #define R8A7793_CLK_VCP0 1 37 #define R8A7793_CLK_VPC0 3 38 #define R8A7793_CLK_SSP1 9 39 #define R8A7793_CLK_TMU1 11 40 #define R8A7793_CLK_3DG 12 41 #define R8A7793_CLK_2DDMAC 15 42 #define R8A7793_CLK_FDP1_1 18 43 #define R8A7793_CLK_FDP1_0 19 44 #define R8A7793_CLK_TMU3 21 45 #define R8A7793_CLK_TMU2 22 46 #define R8A7793_CLK_CMT0 24 47 #define R8A7793_CLK_TMU0 25 48 #define R8A7793_CLK_VSP1_DU1 27 49 #define R8A7793_CLK_VSP1_DU0 28 50 #define R8A7793_CLK_VSP1_S 31 51 52 /* MSTP2 */ 53 #define R8A7793_CLK_SCIFA2 2 54 #define R8A7793_CLK_SCIFA1 3 55 #define R8A7793_CLK_SCIFA0 4 56 #define R8A7793_CLK_MSIOF2 5 57 #define R8A7793_CLK_SCIFB0 6 58 #define R8A7793_CLK_SCIFB1 7 59 #define R8A7793_CLK_MSIOF1 8 60 #define R8A7793_CLK_SCIFB2 16 61 #define R8A7793_CLK_SYS_DMAC1 18 62 #define R8A7793_CLK_SYS_DMAC0 19 63 64 /* MSTP3 */ 65 #define R8A7793_CLK_TPU0 4 66 #define R8A7793_CLK_SDHI2 11 67 #define R8A7793_CLK_SDHI1 12 68 #define R8A7793_CLK_SDHI0 14 69 #define R8A7793_CLK_MMCIF0 15 70 #define R8A7793_CLK_IIC0 18 71 #define R8A7793_CLK_PCIEC 19 72 #define R8A7793_CLK_IIC1 23 73 #define R8A7793_CLK_SSUSB 28 74 #define R8A7793_CLK_CMT1 29 75 #define R8A7793_CLK_USBDMAC0 30 76 #define R8A7793_CLK_USBDMAC1 31 77 78 /* MSTP4 */ 79 #define R8A7793_CLK_IRQC 7 80 #define R8A7793_CLK_INTC_SYS 8 81 82 /* MSTP5 */ 83 #define R8A7793_CLK_AUDIO_DMAC1 1 84 #define R8A7793_CLK_AUDIO_DMAC0 2 85 #define R8A7793_CLK_ADSP_MOD 6 86 #define R8A7793_CLK_THERMAL 22 87 #define R8A7793_CLK_PWM 23 88 89 /* MSTP7 */ 90 #define R8A7793_CLK_EHCI 3 91 #define R8A7793_CLK_HSUSB 4 92 #define R8A7793_CLK_HSCIF2 13 93 #define R8A7793_CLK_SCIF5 14 94 #define R8A7793_CLK_SCIF4 15 95 #define R8A7793_CLK_HSCIF1 16 96 #define R8A7793_CLK_HSCIF0 17 97 #define R8A7793_CLK_SCIF3 18 98 #define R8A7793_CLK_SCIF2 19 99 #define R8A7793_CLK_SCIF1 20 100 #define R8A7793_CLK_SCIF0 21 101 #define R8A7793_CLK_DU1 23 102 #define R8A7793_CLK_DU0 24 103 #define R8A7793_CLK_LVDS0 26 104 105 /* MSTP8 */ 106 #define R8A7793_CLK_IPMMU_SGX 0 107 #define R8A7793_CLK_VIN2 9 108 #define R8A7793_CLK_VIN1 10 109 #define R8A7793_CLK_VIN0 11 110 #define R8A7793_CLK_ETHER 13 111 #define R8A7793_CLK_SATA1 14 112 #define R8A7793_CLK_SATA0 15 113 114 /* MSTP9 */ 115 #define R8A7793_CLK_GPIO7 4 116 #define R8A7793_CLK_GPIO6 5 117 #define R8A7793_CLK_GPIO5 7 118 #define R8A7793_CLK_GPIO4 8 119 #define R8A7793_CLK_GPIO3 9 120 #define R8A7793_CLK_GPIO2 10 121 #define R8A7793_CLK_GPIO1 11 122 #define R8A7793_CLK_GPIO0 12 123 #define R8A7793_CLK_RCAN1 15 124 #define R8A7793_CLK_RCAN0 16 125 #define R8A7793_CLK_QSPI_MOD 17 126 #define R8A7793_CLK_I2C5 25 127 #define R8A7793_CLK_IICDVFS 26 128 #define R8A7793_CLK_I2C4 27 129 #define R8A7793_CLK_I2C3 28 130 #define R8A7793_CLK_I2C2 29 131 #define R8A7793_CLK_I2C1 30 132 #define R8A7793_CLK_I2C0 31 133 134 /* MSTP10 */ 135 #define R8A7793_CLK_SSI_ALL 5 136 #define R8A7793_CLK_SSI9 6 137 #define R8A7793_CLK_SSI8 7 138 #define R8A7793_CLK_SSI7 8 139 #define R8A7793_CLK_SSI6 9 140 #define R8A7793_CLK_SSI5 10 141 #define R8A7793_CLK_SSI4 11 142 #define R8A7793_CLK_SSI3 12 143 #define R8A7793_CLK_SSI2 13 144 #define R8A7793_CLK_SSI1 14 145 #define R8A7793_CLK_SSI0 15 146 #define R8A7793_CLK_SCU_ALL 17 147 #define R8A7793_CLK_SCU_DVC1 18 148 #define R8A7793_CLK_SCU_DVC0 19 149 #define R8A7793_CLK_SCU_CTU1_MIX1 20 150 #define R8A7793_CLK_SCU_CTU0_MIX0 21 151 #define R8A7793_CLK_SCU_SRC9 22 152 #define R8A7793_CLK_SCU_SRC8 23 153 #define R8A7793_CLK_SCU_SRC7 24 154 #define R8A7793_CLK_SCU_SRC6 25 155 #define R8A7793_CLK_SCU_SRC5 26 156 #define R8A7793_CLK_SCU_SRC4 27 157 #define R8A7793_CLK_SCU_SRC3 28 158 #define R8A7793_CLK_SCU_SRC2 29 159 #define R8A7793_CLK_SCU_SRC1 30 160 #define R8A7793_CLK_SCU_SRC0 31 161 162 /* MSTP11 */ 163 #define R8A7793_CLK_SCIFA3 6 164 #define R8A7793_CLK_SCIFA4 7 165 #define R8A7793_CLK_SCIFA5 8 166 167 #endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ 168