| /external/boringssl/src/ssl/test/runner/curve25519/ |
| D | cswap_amd64.s | 20 MOVQ SI,R9
22 CMOVQEQ R9,DX
23 MOVQ CX,R9
25 CMOVQEQ R9,R8
34 MOVQ SI,R9
36 CMOVQEQ R9,DX
37 MOVQ CX,R9
39 CMOVQEQ R9,R8
48 MOVQ SI,R9
50 CMOVQEQ R9,DX
[all …]
|
| D | ladderstep_amd64.s | 20 MOVQ 72(DI),R9
25 MOVQ R9,R13
35 ADDQ 112(DI),R9
45 MOVQ R9,32(SP)
59 MOVQ DX,R9
107 ADCQ DX,R9
112 ADCQ DX,R9
126 SHLQ $13,R9:R8
131 ADDQ R9,R10
148 MOVQ CX,R9
[all …]
|
| D | square_amd64.s | 24 MOVQ AX,R9
72 ADDQ AX,R9
77 ADDQ AX,R9
92 SHLQ $13,R10:R9
93 ANDQ SI,R9
94 ADDQ R8,R9
108 ADDQ R9,DX
114 MOVQ DX,R9
117 ANDQ SI,R9
129 MOVQ R9,16(DI)
|
| D | freeze_amd64.s | 20 MOVQ 32(DI),R9
41 ADDQ R12,R9
42 MOVQ R9,R12
44 ANDQ AX,R9
58 CMPQ AX,R9
67 SUBQ AX,R9
72 MOVQ R9,32(DI)
|
| D | mul_amd64.s | 24 MOVQ DX,R9
30 ADCQ DX,R9
34 ADCQ DX,R9
71 ADCQ DX,R9
88 ADCQ DX,R9
127 SHLQ $13,R9:R8
131 ADDQ R9,R10
150 MOVQ DX,R9
156 ANDQ SI,R9
166 MOVQ R9,16(DI)
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_tns_parcor2lpc_32x16.s | 42 MOV R9, #0x7FFFFFFF
43 MOV R10, R9, ASR R8
78 LDRSH R9, [R4, #-2]!
80 MOV R9, R9, LSL #16
84 QADD R9, R9, R2
86 QADD R14, R9, R5
87 MOVS R9, R9
90 @ RSBMIS R9, R9, #0
91 RSBSMI R9, R9, #0
92 MOVMI R9, #0x7FFFFFFF
[all …]
|
| D | ixheaacd_sbr_qmfsyn64_winadd.s | 52 MOV R9, R7, LSL #1
53 ADD R1, R1, R9
56 MOV R9, R7, LSL #1
66 VLD1.16 D3, [R2], R9
71 VLD1.16 D5, [R2], R9
76 VLD1.16 D7, [R2], R9
81 VLD1.16 D9, [R2], R9
100 VLD1.16 D13, [R12], R9
105 VLD1.16 D15, [R12], R9
110 VLD1.16 D17, [R12], R9
[all …]
|
| D | ixheaacd_esbr_qmfsyn64_winadd.s | 39 MOV R9, R7, LSL #1
40 ADD R1, R1, R9
43 MOV R9, R7, LSL #1 @(256*2)
55 VLD1.32 {D6, D7}, [R2], R9
61 VLD1.32 {D10, D11}, [R2], R9
67 VLD1.32 {D14, D15}, [R2], R9
73 VLD1.32 {D18, D19}, [R2], R9
93 VLD1.32 {D6, D7}, [R12], R9
99 VLD1.32 {D10, D11}, [R12], R9
105 VLD1.32 {D14, D15}, [R12], R9
[all …]
|
| D | ixheaacd_apply_rot.s | 36 ADD R9, R5, R6
37 STRH R9, [R11, #-98]
46 ADD R9, R5, R6
47 STRH R9, [R11, #-2]
55 ADD R9, R5, R6
56 STRH R9, [R11, #-98]
66 ADD R9, R5, R6
67 STRH R9, [R11, #-2]
85 SMULWB R9, R5, R7
89 QADD R5, R9, R10
[all …]
|
| D | ixheaacd_cos_sin_mod.s | 67 ADD R9, R0, R6
70 LDR R1, [R9], #-4
104 LDR R1, [R9, #0x104]
120 LDR R0, [R9], #-4
129 LDR R0, [R9, #0x104]
144 LDR R1, [R9], #-4
166 LDR R1, [R9, #0x104]
182 LDR R0, [R9], #-4
190 LDR R0, [R9, #0x104]
204 LDRGT R1, [R9], #-4
[all …]
|
| D | ixheaacd_conv_ergtoamplitude.s | 39 MOV R9, #-16
58 MOV R9, R7, ASR #1
61 STRH R9, [R2, #-2]
67 MOV R9, #-16
85 MOV R9, R7, ASR #1
88 STRH R9, [R3, #-2]
95 MOV R9, #-16
113 MOV R9, R7, ASR #1
115 STRH R9, [R4, #-2]
117 SUB R6, R1, R9
|
| D | ixheaacd_post_twiddle_overlap.s | 35 LSL R9, R3, #2
36 ASR R9, R9, #1
37 ADD R6, R6, R9
46 RSB R9, R5, #15
52 LSL R8, R8, R9
60 LDR R9, [R1], #4
65 SMULWB R12, R9, R10
67 SMLAWT R7, R9, R10, R5
72 MOV R9, #50
74 SMULWB R10, R5, R9
[all …]
|
| D | ixheaacd_overlap_add1.s | 63 MOV R9, R6, LSL #1
132 VST1.16 D18[0], [R6], R9
134 VST1.16 D18[1], [R6], R9
136 VST1.16 D18[2], [R6], R9
138 VST1.16 D18[3], [R6], R9
186 VST1.16 D18[0], [R6], R9
188 VST1.16 D18[1], [R6], R9
190 VST1.16 D18[2], [R6], R9
200 VST1.16 D18[3], [R6], R9
243 VST1.16 D18[0], [R6], R9
[all …]
|
| D | ixheaacd_conv_ergtoamplitudelp.s | 63 MOV R9, #-16
80 MOV R9, R7, ASR #1
84 STRH R9, [R3, #2]
92 MOV R9, #-16
108 MOV R9, R7, ASR #1
112 STRH R9, [R4, #2]
114 SUB R6, R1, R9
|
| D | ixheaacd_sbr_qmfanal32_winadds.s | 34 MOV R9, R7, LSL #1
77 MOV R9, R0
112 MOV R0, R9
122 MOV R9, R1
152 MOV R1, R9
165 MOV R9, R0
206 MOV R0, R9
215 MOV R9, R1
244 MOV R1, R9
|
| D | ia_xheaacd_mps_reoder_mulshift_acc.s | 41 MUL R9, R5, R10
48 SUBS R9, R9, #8
56 MOV R9, R1
60 VLD1.32 {Q2, Q3}, [R9]! @LOADING values from R1 Si_fix
100 MOV R9, R1
104 VLD1.32 {Q2, Q3}, [R9]! @LOADING values from R1 Si_fix
143 MOV R9, R1
148 VLD1.32 {Q2, Q3}, [R9]! @LOADING values from R1 Si_fix
187 MOV R9, R1
192 VLD1.32 {Q2, Q3}, [R9]! @LOADING values from R1 Si_fix
|
| D | ixheaacd_pre_twiddle_compute.s | 45 LDR R9, [R0], #4
47 SMULWB R12, R9, R8
49 SMULWT R11, R9, R8
50 SMLAWT R9, R10, R8, R12
53 MVN R9, R9
54 ADD R9, R9, #1
63 ASR R9, R9, R8
68 LSL R9, R9, R5
73 STR R9, [R2], #4
|
| D | ixheaacd_sbr_qmfanal32_winadds_eld.s | 12 MOV R9, R7, LSL #1
56 MOV R9, R0
90 MOV R0, R9
100 MOV R9, R1
132 MOV R1, R9
145 MOV R9, R0
187 MOV R0, R9
196 MOV R9, R1
226 MOV R1, R9
|
| D | ixheaacd_rescale_subbandsamples.s | 37 ADD R9, R0, R5, LSL#2
38 LDR R10, [R9], #4
71 LDR R10, [R9], #4
96 LDR R10, [R9], #4
150 LDR R10, [R9], #4
196 LDR R10, [R9], #4
|
| D | ixheaacd_dct3_32.s | 38 MOV R9, #0
39 VDUP.32 D0, R9
55 SUB R9, R6, #144
64 VLD1.32 {Q3}, [R9]!
107 SUB R9, R6, #144
114 VLD1.32 {Q3}, [R9]!
142 SUB R9, R6, #144
145 VLD1.32 {Q3}, [R9]!
187 SUB R9, R6, #140
191 VLD1.32 D6, [R9]!
[all …]
|
| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | sum_arm.s | 32 MOVW R2>>26, R9
36 ORR R3<<6, R9, R9
41 AND R9, R3, R3
88 MOVM.IA (R0), [R0-R9]
128 ADD R4, R9, R9
140 MULALU R0, R9, (R11, g)
141 MULALU R4, R9, (R14, R12)
156 MULALU R3, R9, (R11, g)
157 MULALU R2, R9, (R14, R12)
166 MULALU R1, R9, (R11, g)
[all …]
|
| D | sum_amd64.s | 73 XORQ R9, R9 // h1
80 POLY1305_ADD(SI, R8, R9, R10)
83 POLY1305_MUL(R8, R9, R10, R11, R12, BX, CX, R13, R14)
106 ADCQ CX, R9
113 MOVQ R9, BX
118 CMOVQCS R9, BX
|
| /external/libdrm/data/ |
| D | amdgpu.ids | 24 6640, 80, AMD Radeon (TM) R9 M380
25 6646, 0, AMD Radeon R9 M280X
26 6646, 80, AMD Radeon (TM) R9 M470X
27 6647, 0, AMD Radeon R9 M270X
28 6647, 80, AMD Radeon (TM) R9 M380
52 67B0, 0, AMD Radeon R9 200 Series
53 67B0, 80, AMD Radeon (TM) R9 390 Series
54 67B1, 0, AMD Radeon R9 200 Series
55 67B1, 80, AMD Radeon (TM) R9 390 Series
56 67B9, 0, AMD Radeon R9 200 Series
[all …]
|
| /external/syzkaller/vendor/golang.org/x/sys/unix/ |
| D | asm_linux_ppc64x.s | 32 MOVD trap+0(FP), R9 // syscall entry
33 SYSCALL R9
52 MOVD trap+0(FP), R9 // syscall entry
53 SYSCALL R9
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | atomic.ll | 86 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
90 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
117 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
121 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
148 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
152 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
180 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
185 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
210 ; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
217 ; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
|