Searched refs:RADEON_PP_CNTL (Results 1 – 9 of 9) sorted by relevance
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_blit.c | 168 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | in emit_tx_setup()
189 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | in emit_tx_setup()
219 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | in emit_tx_setup()
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| D | r200_state_init.c | 64 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
506 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); in ctx_emit_cs()
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| D | r200_sanity.c | 68 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_ioctl.c | 102 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
113 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
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| D | radeon_sanity.c | 64 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
173 { RADEON_PP_CNTL, "RADEON_PP_CNTL" },
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| D | radeon_blit.c | 135 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); in emit_tx_setup()
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| D | radeon_state_init.c | 59 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
388 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); in ctx_emit_cs()
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| /external/mesa3d/src/mesa/drivers/dri/r200/server/ |
| D | radeon_reg.h | 1141 #define RADEON_PP_CNTL 0x1c38 macro
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| /external/mesa3d/src/mesa/drivers/dri/radeon/server/ |
| D | radeon_reg.h | 1141 #define RADEON_PP_CNTL 0x1c38 macro
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