/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrSPE.td | 19 bits<5> RB; 25 let Inst{16-20} = RB; 31 let RB = 0; 38 bits<5> RB; 45 let Inst{16-20} = RB; 113 let RB = 0; 116 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 117 "brinc $RT, $RA, $RB", IIC_VecFP>; 121 def EVADDIW : EVXForm_1<514, (outs gprc:$RT), (ins gprc:$RA, u5imm:$RB), 122 "evaddiw $RT, $RB, $RA", IIC_VecFP>; [all …]
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D | p9-instrs.txt | 63 [PO BF / L RA RB XO /] cmprb BF,L,RA,RB 66 [PO BF // RA RB XO /] cmpeqb BF,RA,RB 81 [PO /// L RA RB XO /] copy RA,RB,L 82 copy_first = copy RA, RB, 1 87 [PO /// L RA RB XO Rc] paste(.) RA,RB,L 88 paste_last = paste RA,RB,1 96 [PO RT RA RB RC XO] maddhd RT,RA.RB,RC 99 [PO RT RA RB RC XO] maddhdu RT,RA.RB,RC 102 [PO RT RA RB RC XO] maddld RT,RA.RB,RC 105 [PO RT RA RB XO /] modsw RT,RA,RB [all …]
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D | PPCInstrHTM.td | 109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB), 110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>; 115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB), 116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCInstrSPE.td | 20 bits<5> RB; 26 let Inst{16-20} = RB; 33 let RB = 0; 47 bits<5> RB; 52 let Inst{16-20} = RB; 61 bits<5> RB; 67 let Inst{16-20} = RB; 74 let RB = 0; 88 bits<5> RB; 95 let Inst{16-20} = RB; [all …]
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D | PPCInstrHTM.td | 109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB), 110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>; 115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB), 116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaInstrInfo.td | 228 def Lr : OForm< opc, funl, !strconcat(asmstr, "l $RA,$RB,$RC"), 229 [(set GPRC:$RC, (intop (OpNode GPRC:$RA, GPRC:$RB)))], itin>; 232 def Qr : OForm< opc, funq, !strconcat(asmstr, "q $RA,$RB,$RC"), 233 [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>; 254 def r : OForm<opc, fun, !strconcat(asmstr, " $RA,$RB,$RC"), 255 [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>; 260 def r : OForm<opc, fun, !strconcat(asmstr, " $RA,$RB,$RC"), 261 [(set GPRC:$RC, (OpNode GPRC:$RA, (not GPRC:$RB)))], itin>; 278 def CTLZ : OForm2<0x1C, 0x32, "CTLZ $RB,$RC", 279 [(set GPRC:$RC, (ctlz GPRC:$RB))], s_imisc>; [all …]
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/external/clang/lib/Rewrite/ |
D | HTMLRewrite.cpp | 57 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E, in HighlightRange() argument 61 RB.InsertTextAfter(B, StartTag); in HighlightRange() 62 RB.InsertTextBefore(E, EndTag); in HighlightRange() 76 RB.InsertTextBefore(LastNonWhiteSpace+1, EndTag); in HighlightRange() 95 RB.InsertTextAfter(i, StartTag); in HighlightRange() 115 RewriteBuffer &RB = R.getEditBuffer(FID); in EscapeText() local 128 RB.ReplaceText(FilePos, 1, " "); in EscapeText() 132 RB.ReplaceText(FilePos, 1, "<hr>"); in EscapeText() 141 RB.ReplaceText(FilePos, 1, in EscapeText() 145 RB.ReplaceText(FilePos, 1, StringRef(" ", NumSpaces)); in EscapeText() [all …]
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D | Rewriter.cpp | 143 const RewriteBuffer &RB = I->second; in getRangeSize() local 144 EndOff = RB.getMappedOffset(EndOff, opts.IncludeInsertsAtEndOfRange); in getRangeSize() 145 StartOff = RB.getMappedOffset(StartOff, !opts.IncludeInsertsAtBeginOfRange); in getRangeSize() 195 const RewriteBuffer &RB = I->second; in getRewrittenText() local 196 EndOff = RB.getMappedOffset(EndOff, true); in getRewrittenText() 197 StartOff = RB.getMappedOffset(StartOff); in getRewrittenText() 204 RewriteBuffer::iterator Start = RB.begin(); in getRewrittenText() 381 RewriteBuffer &RB = getEditBuffer(FID); in IncreaseIndentation() local 389 RB.InsertText(offs, indent, /*InsertAfter=*/false); in IncreaseIndentation()
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/external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
D | instructions.h | 9 #define __COPY(RA, RB, L) \ argument 10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10)) 11 #define COPY(RA, RB, L) \ argument 12 .long __COPY((RA), (RB), (L)) 33 #define __PASTE(RA, RB, L, RC) \ argument 34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31)) 35 #define PASTE(RA, RB, L, RC) \ argument 36 .long __PASTE((RA), (RB), (L), (RC))
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRDF.cpp | 19 bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() 20 if (RA == RB) in covers() 24 TargetRegisterInfo::isVirtualRegister(RB.Reg)) { in covers() 26 if (RA.Reg == RB.Reg) { in covers() 29 if (RB.Sub == 0) in covers() 34 return RegisterAliasInfo::covers(RA, RB); in covers()
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D | RDFGraph.cpp | 573 bool RegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() 574 if (RA == RB) in covers() 577 assert(TargetRegisterInfo::isVirtualRegister(RB.Reg)); in covers() 578 if (RA.Reg != RB.Reg) in covers() 582 return TRI.composeSubRegIndices(RA.Sub, RB.Sub) == RA.Sub; in covers() 586 TargetRegisterInfo::isPhysicalRegister(RB.Reg)); in covers() 588 unsigned B = RB.Sub != 0 ? TRI.getSubReg(RB.Reg, RB.Sub) : RB.Reg; in covers() 634 bool RegisterAliasInfo::alias(RegisterRef RA, RegisterRef RB) const { in alias() 636 bool VirtB = TargetRegisterInfo::isVirtualRegister(RB.Reg); in alias() 638 bool PhysB = TargetRegisterInfo::isPhysicalRegister(RB.Reg); in alias() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | RDFRegisters.h | 116 bool alias(RegisterRef RA, RegisterRef RB) const { in alias() 118 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); in alias() 119 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); in alias() 153 bool aliasRR(RegisterRef RA, RegisterRef RB) const; 167 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf() 169 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
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/external/clang/test/Layout/ |
D | ms-x86-alias-avoidance-padding.cpp | 302 struct RB { char c; }; argument 306 struct RX0 : RB, RA {}; 307 struct RX1 : RA, RB {}; 309 struct RX3 : RA { RB a; }; 311 struct RX5 { RA a; RB b; }; 312 struct RX6 : virtual RV { RB a; };
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/external/linux-kselftest/tools/testing/selftests/powerpc/context_switch/ |
D | cp_abort.c | 36 #define PASTE(RA, RB, L, RC) \ argument 37 .long (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31)) 53 #define COPY(RA, RB, L) \ argument 54 .long (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
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/external/clang/lib/Frontend/Rewrite/ |
D | RewriteMacros.cpp | 95 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID()); in RewriteMacrosInInput() local 134 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput() 140 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput() 170 RB.InsertTextAfter(RawOffs, &" /*"[HasSpace]); in RewriteMacrosInInput() 188 RB.InsertTextBefore(EndPos, "*/"); in RewriteMacrosInInput() 204 RB.InsertTextBefore(InsertPos, Expansion); in RewriteMacrosInInput()
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
D | MBlazeDisassembler.cpp | 527 unsigned RB = getRB(insn); in getInstruction() local 536 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction() 539 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction() 544 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction() 548 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction() 595 if (RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction() 598 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction() 609 if (RD == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction() 612 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction() 623 if (RB == UNSUPPORTED) in getInstruction() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64InstructionSelector.cpp | 142 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() argument 145 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank() 155 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank() 394 const RegisterBank *RB = nullptr; in selectCopy() local 396 RB = RegClassOrBank.get<const RegisterBank *>(); in selectCopy() 397 SrcRC = getRegClassForTypeOnBank(MRI.getType(SrcReg), *RB, RBI, true); in selectCopy() 605 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI); in selectCompareBranch() local 606 if (RB.getID() != AArch64::GPRRegBankID) in selectCompareBranch() 736 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select() local 737 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPUInstrFormats.td | 33 bits<7> RB; 39 let Inst{11-17} = RB; 44 let RB = 0 in { 45 // RR Format, where RB is zeroed (dont care): 52 // RR Format, where RA and RB are zeroed (dont care): 76 bits<7> RB; 84 let Inst{11-17} = RB; 139 let RB = 0 in {
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/ |
D | insert-element-build-vector.ll | 15 ; CHECK-NEXT: [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP4]], i32 1 17 ; CHECK-NEXT: [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[TMP5]], i32 2 28 ; ZEROTHRESH-NEXT: [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP4]], i32 1 30 ; ZEROTHRESH-NEXT: [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[TMP5]], i32 2 88 ; CHECK-NEXT: [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[S1]], i32 1 89 ; CHECK-NEXT: [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[S2]], i32 2 124 ; ZEROTHRESH-NEXT: [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[S1]], i32 1 125 ; ZEROTHRESH-NEXT: [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[S2]], i32 2 183 ; CHECK-NEXT: [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP4]], i32 1 185 ; CHECK-NEXT: [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[TMP5]], i32 0 [all …]
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/external/llvm/lib/CodeGen/GlobalISel/ |
D | RegisterBankInfo.cpp | 70 RegisterBank &RB = getRegBank(ID); in addRegBankCoverage() local 73 DEBUG(dbgs() << "Add coverage for: " << RB << '\n'); in addRegBankCoverage() 76 if (!RB.isValid()) in addRegBankCoverage() 77 RB.ContainedRegClasses.resize(NbOfRegClasses); in addRegBankCoverage() 78 else if (RB.covers(*TRI.getRegClass(RCId))) in addRegBankCoverage() 83 BitVector &Covered = RB.ContainedRegClasses; in addRegBankCoverage() 89 unsigned &MaxSize = RB.Size; in addRegBankCoverage()
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/external/python/cpython3/Lib/test/ |
D | tokenize_tests.txt | 117 x = rb'abc' + rB'ABC' + Rb'ABC' + RB'ABC' 118 y = rb"abc" + rB"ABC" + Rb"ABC" + RB"ABC" 120 x = rb'\\' + RB'\\'
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenRegisterBank.inc | 73 for (const auto &RB : RegBanks) 74 assert(Index++ == RB->getID() && "Index != ID");
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/external/pdfium/third_party/libtiff/ |
D | tif_color.c | 178 #define Code2V(c, RB, RW, CR) ((((c)-(int32)(RB))*(float)(CR))/(float)(((RW)-(RB)!=0) ? ((RW)-(RB))… argument
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenRegisterBank.inc | 94 for (const auto &RB : RegBanks) 95 assert(Index++ == RB->getID() && "Index != ID");
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86InstructionSelector.cpp | 73 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc, 127 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const; 169 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass() 170 if (RB.getID() == X86::GPRRegBankID) { in getRegClass() 180 if (RB.getID() == X86::VECRRegBankID) { in getRegClass() 392 const RegisterBank &RB, in getLoadStoreOp() argument 401 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp() 404 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp() 407 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp() 409 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp() [all …]
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