| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 213 int RCID = Desc.OpInfo[i].RegClass; in encodeInstruction() local
214 const MCRegisterClass &RC = MRI.getRegClass(RCID); in encodeInstruction()
283 int RCID = Desc.OpInfo[OpNo].RegClass; in getMachineOpValue() local
284 const MCRegisterClass &RC = MRI.getRegClass(RCID); in getMachineOpValue()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 98 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
99 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
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| D | SIInstrInfo.cpp | 1860 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
1861 return RI.getRegClass(RCID); in getOpRegClass()
1881 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
1882 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
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| D | AMDGPUISelDAGToDAG.cpp | 207 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
209 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 137 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
138 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
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| D | SIInstrInfo.cpp | 3058 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
3059 return RI.getRegClass(RCID); in getOpRegClass()
3079 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
3080 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
5015 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local
5016 return RCID == AMDGPU::SReg_128RegClassID; in isBufferSMRD()
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| D | AMDGPUISelDAGToDAG.cpp | 340 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
342 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 789 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
790 switch (RCID) { in getRegBitWidth()
826 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
827 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
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| D | AMDGPUBaseInfo.h | 384 unsigned getRegBitWidth(unsigned RCID);
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineInstr.cpp | 879 unsigned RCID; in getRegClassConstraint() local
880 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
881 return TRI->getRegClass(RCID); in getRegClassConstraint()
1475 unsigned RCID = 0; in print() local
1476 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1478 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); in print()
1480 OS << ":RC" << RCID; in print()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 675 unsigned RCID; in getRegClassConstraint() local
679 InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
680 return TRI->getRegClass(RCID); in getRegClassConstraint()
1434 unsigned RCID = 0; in print() local
1436 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1438 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1440 OS << ":RC" << RCID; in print()
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1203 unsigned RCID; in getRegClassConstraint() local
1204 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
1205 return TRI->getRegClass(RCID); in getRegClassConstraint()
1828 unsigned RCID = 0; in print() local
1829 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1831 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1833 OS << ":RC" << RCID; in print()
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 386 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
387 if (RCID != -1) { in printOperand()
388 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID); in printOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 344 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst() local
353 &MRI.getRegClass(RCID)); in convertMIMGInst()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 246 bool isRegClass(unsigned RCID) const { in isRegClass()
247 return isReg() && Reg.TRI->getRegClass(RCID).contains(getReg()); in isRegClass()
932 int RCID = getRegClass(RegKind, RegWidth); in ParseAMDGPURegister() local
933 if (RCID == -1) in ParseAMDGPURegister()
935 const MCRegisterClass RC = TRI->getRegClass(RCID); in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 341 bool isRegClass(unsigned RCID) const;
343 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
344 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers(); in isRegOrInlineNoMods()
1340 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
1341 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
1790 int RCID = getRegClass(RegKind, RegWidth); in ParseAMDGPURegister() local
1791 if (RCID == -1) in ParseAMDGPURegister()
1793 const MCRegisterClass RC = TRI->getRegClass(RCID); in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 567 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
568 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()
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| /external/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1467 unsigned RCID; in handleSpecialFP() local
1485 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1515 unsigned RCID; in handleSpecialFP() local
1533 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()
|