| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 28 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() local
29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
96 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print() local
97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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| D | RegisterBankInfo.cpp | 67 void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId, in addRegBankCoverage() argument
78 else if (RB.covers(*TRI.getRegClass(RCId))) in addRegBankCoverage()
86 WorkList.push_back(RCId); in addRegBankCoverage()
87 Covered.set(RCId); in addRegBankCoverage()
91 unsigned RCId = WorkList.pop_back_val(); in addRegBankCoverage() local
93 const TargetRegisterClass &CurRC = *TRI.getRegClass(RCId); in addRegBankCoverage()
149 if (SuperRCId == RCId) { in addRegBankCoverage()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() local
34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
103 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print() local
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineLICM.cpp | 231 unsigned &RCId, unsigned &RCCost) const;
670 unsigned &RCId, unsigned &RCCost) const { in getRegisterClassIDAndCost() argument
674 RCId = RC->getID(); in getRegisterClassIDAndCost()
677 RCId = TLI->getRepRegClassFor(VT)->getID(); in getRegisterClassIDAndCost()
711 unsigned RCId, RCCost; in InitRegPressure() local
712 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost); in InitRegPressure()
714 RegPressure[RCId] += RCCost; in InitRegPressure()
719 RegPressure[RCId] += RCCost; in InitRegPressure()
721 RegPressure[RCId] -= RCCost; in InitRegPressure()
746 unsigned RCId, RCCost; in UpdateRegPressure() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 68 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
105 unsigned RCId) { in numberRCValSuccInSU() argument
132 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
318 int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { in rawRegPressureDelta() argument
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
330 RegBalance += numberRCValSuccInSU(SU, RCId); in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
341 RegBalance -= numberRCValPredInSU(SU, RCId); in rawRegPressureDelta()
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| D | ScheduleDAGRRList.cpp | 2081 unsigned RCId, Cost; in HighRegPressure() local
2082 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); in HighRegPressure()
2084 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
2102 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in MayReduceRegPressure() local
2103 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2133 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2134 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2148 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2149 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2193 unsigned RCId, Cost; in scheduledNode() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ResourcePriorityQueue.h | 113 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
131 unsigned numberRCValPredInSU (SUnit *SU, unsigned RCId);
132 unsigned numberRCValSuccInSU (SUnit *SU, unsigned RCId);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
98 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
108 unsigned RCId) { in numberRCValSuccInSU() argument
136 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
326 int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { in rawRegPressureDelta() argument
337 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
338 RegBalance += numberRCValSuccInSU(SU, RCId); in rawRegPressureDelta()
348 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
349 RegBalance -= numberRCValPredInSU(SU, RCId); in rawRegPressureDelta()
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| D | ScheduleDAGRRList.cpp | 1957 unsigned RCId, Cost; in HighRegPressure() local
1958 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); in HighRegPressure()
1960 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1978 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in MayReduceRegPressure() local
1979 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2009 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2010 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2024 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2025 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2069 unsigned RCId, Cost; in scheduledNode() local
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ResourcePriorityQueue.h | 113 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
131 unsigned numberRCValPredInSU (SUnit *SU, unsigned RCId);
132 unsigned numberRCValSuccInSU (SUnit *SU, unsigned RCId);
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1847 unsigned RCId, Cost; in HighRegPressure() local
1848 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost); in HighRegPressure()
1850 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1868 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in MayReduceRegPressure() local
1869 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
1900 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
1901 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
1915 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
1916 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
1961 unsigned RCId, Cost; in ScheduledNode() local
[all …]
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| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| D | NVPTXInstPrinter.cpp | 38 unsigned RCId = (RegNo >> 28); in printRegName() local
39 switch (RCId) { in printRegName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/InstPrinter/ |
| D | NVPTXInstPrinter.cpp | 38 unsigned RCId = (RegNo >> 28); in printRegName() local
39 switch (RCId) { in printRegName()
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| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 345 void addRegBankCoverage(unsigned ID, unsigned RCId,
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| /external/clang/lib/Sema/ |
| D | SemaExprObjC.cpp | 3856 IdentifierInfo *RCId = ObjCBAttr->getRelatedClass(); in checkObjCBridgeRelatedComponents() local
3859 if (!RCId) in checkObjCBridgeRelatedComponents()
3863 LookupResult R(*this, DeclarationName(RCId), SourceLocation(), in checkObjCBridgeRelatedComponents()
3867 Diag(Loc, diag::err_objc_bridged_related_invalid_class) << RCId in checkObjCBridgeRelatedComponents()
3878 Diag(Loc, diag::err_objc_bridged_related_invalid_class_name) << RCId in checkObjCBridgeRelatedComponents()
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