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Searched refs:RDLVL_GATE_EN (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Ddmc_init_ddr3.c166 val |= RDLVL_GATE_EN; in ddr3_mem_ctrl_init()
730 setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN); in ddr3_mem_ctrl_init()
731 setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN); in ddr3_mem_ctrl_init()
Dexynos5_setup.h268 #define RDLVL_GATE_EN (1 << 24) macro