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Searched refs:REGS (Results 1 – 4 of 4) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopStrengthReduce/X86/
Dlsr-insns-1.ll4 …educe -mtriple=x86_64 -lsr-insns-cost=false -S | FileCheck %s -check-prefix=BOTH -check-prefix=REGS
51 ; REGS-LABEL: @foo(
52 ; REGS-NEXT: entry:
53 ; REGS-NEXT: br label [[FOR_BODY:%.*]]
54 ; REGS: for.cond.cleanup:
55 ; REGS-NEXT: ret void
56 ; REGS: for.body:
57 ; REGS-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR…
58 ; REGS-NEXT: [[SCEVGEP2:%.*]] = getelementptr i32, i32* [[X:%.*]], i64 [[INDVARS_IV]]
59 ; REGS-NEXT: [[TMP:%.*]] = load i32, i32* [[SCEVGEP2]], align 4
[all …]
Dlsr-insns-2.ll2 …educe -mtriple=x86_64 -lsr-insns-cost=false -S | FileCheck %s -check-prefix=BOTH -check-prefix=REGS
13 ; REGS %lsr.iv4 = phi
14 ; REGS %lsr.iv2 = phi
15 ; REGS %lsr.iv1 = phi
16 ; REGS: getelementptr i32, i32* %lsr.iv1, i64 1
17 ; REGS: getelementptr i32, i32* %lsr.iv2, i64 1
18 ; REGS: getelementptr i32, i32* %lsr.iv4, i64 1
/external/elfutils/libcpu/
Dbpf_disasm.c57 #define REGS(N) "(s64)" REG(N) macro
344 code_fmt = J64(REGS(1), >, IMMS(2)); in bpf_disasm()
347 code_fmt = J64(REGS(1), >=, IMMS(2)); in bpf_disasm()
356 code_fmt = J64(REGS(1), <, IMMS(2)); in bpf_disasm()
359 code_fmt = J64(REGS(1), <=, IMMS(2)); in bpf_disasm()
378 code_fmt = J64(REGS(1), >, REGS(2)); in bpf_disasm()
381 code_fmt = J64(REGS(1), >=, REGS(2)); in bpf_disasm()
390 code_fmt = J64(REGS(1), <, REGS(2)); in bpf_disasm()
393 code_fmt = J64(REGS(1), <=, REGS(2)); in bpf_disasm()
/external/libpcap/msdos/
Dpktdrvr.c320 union REGS r; in PktInterrupt()
1285 union REGS r; in dpmi_get_real_vector()
1295 union REGS r; in dpmi_real_malloc()
1309 union REGS r; in dpmi_real_free()