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Searched refs:REG_CPU_DIV_CLK_CTRL_0_ADDR (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_dfs.c273 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
315 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
334 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
569 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
609 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
628 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
876 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
914 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
933 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
1288 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
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Dddr3_axp.h350 #define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700 macro