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Searched refs:REG_DDR3_MR1_WL_ENA_OFFS (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp.h271 #define REG_DDR3_MR1_WL_ENA_OFFS 7 macro
Dddr3_write_leveling.c751 reg |= (1 << REG_DDR3_MR1_WL_ENA_OFFS); in ddr3_write_leveling_sw()
988 reg |= (1 << REG_DDR3_MR1_WL_ENA_OFFS); in ddr3_write_leveling_sw_reg_dimm()