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Searched refs:REG_DRAM_PHY_CONFIG_ADDR (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_dfs.c641 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_high_2_low()
644 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
646 reg = (reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK); in ddr3_dfs_high_2_low()
649 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
1016 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
1019 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1022 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
1025 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1366 reg = (reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK); in ddr3_dfs_low_2_high()
1369 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
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Dddr3_axp.h289 #define REG_DRAM_PHY_CONFIG_ADDR 0x15EC macro
Dddr3_init.c119 debug_print_reg(REG_DRAM_PHY_CONFIG_ADDR); in print_dunit_setup()
Dddr3_spd.c1184 reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg);