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Searched refs:REG_DRAM_TRAINING_2_ADDR (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_write_leveling.c218 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_wl_supplement()
223 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
251 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
258 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
400 (reg_read(REG_DRAM_TRAINING_2_ADDR) in ddr3_wl_supplement()
403 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
450 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_wl_supplement()
453 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
704 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_write_leveling_sw()
708 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_write_leveling_sw()
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Dddr3_read_leveling.c188 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
193 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
207 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
211 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
298 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
301 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
304 reg = (reg_read(REG_DRAM_TRAINING_2_ADDR)) & in ddr3_read_leveling_sw()
309 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
311 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
318 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
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Dddr3_pbs.c108 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_tx()
112 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
159 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
163 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
285 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
287 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
381 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_tx()
384 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
551 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_rx()
555 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
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Dddr3_dqs.c138 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_rx()
143 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
158 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
162 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
187 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
189 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
193 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_dqs_centralization_rx()
196 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
220 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_tx()
225 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
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Dddr3_hw_training.c624 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_load_patterns()
629 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
643 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_load_patterns()
646 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
929 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_training_suspend_resume()
935 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_training_suspend_resume()
Dddr3_sdram.c648 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_reset_phy_read_fifo()
654 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_reset_phy_read_fifo()
657 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_reset_phy_read_fifo()
Dddr3_axp.h231 #define REG_DRAM_TRAINING_2_ADDR 0x15B8 macro