Home
last modified time | relevance | path

Searched refs:REG_DRAM_TRAINING_ADDR (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_hw_training.c632 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_load_patterns()
674 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_load_patterns()
679 if (reg_read(REG_DRAM_TRAINING_ADDR) & in ddr3_load_patterns()
923 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_training_suspend_resume()
927 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_training_suspend_resume()
939 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_training_suspend_resume()
942 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_training_suspend_resume()
Dddr3_sdram.c641 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
646 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
661 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
667 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
Dddr3_write_leveling.c87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
99 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_write_leveling_hw()
226 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_wl_supplement()
510 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw_reg_dimm()
522 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_write_leveling_hw_reg_dimm()
632 reg_write(REG_DRAM_TRAINING_ADDR, 0); in ddr3_write_leveling_hw_reg_dimm()
Dddr3_pbs.c116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx()
559 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_rx()
673 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_pbs_rx()
677 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
691 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_pbs_rx()
695 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
Dddr3_read_leveling.c76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
198 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
314 reg_write(REG_DRAM_TRAINING_ADDR, 0); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
Dddr3_axp.h209 #define REG_DRAM_TRAINING_ADDR 0x15B0 macro
Dddr3_dqs.c147 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_rx()
229 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_tx()