Home
last modified time | relevance | path

Searched refs:REG_DRAM_TRAINING_AUTO_OFFS (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_write_leveling.c90 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw()
96 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw()
225 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_wl_supplement()
513 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw_reg_dimm()
519 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_write_leveling_hw_reg_dimm()
Dddr3_read_leveling.c79 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_read_leveling_hw()
85 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_read_leveling_hw()
197 (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_read_leveling_sw()
Dddr3_axp.h222 #define REG_DRAM_TRAINING_AUTO_OFFS 31 macro
Dddr3_hw_training.c631 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_load_patterns()
672 reg |= (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_load_patterns()
Dddr3_dqs.c146 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_dqs_centralization_rx()
228 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS); in ddr3_dqs_centralization_tx()
Dddr3_pbs.c115 reg = 1 << REG_DRAM_TRAINING_AUTO_OFFS; in ddr3_pbs_tx()
558 reg = 1 << REG_DRAM_TRAINING_AUTO_OFFS; in ddr3_pbs_rx()