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Searched refs:REG_DRAM_TRAINING_CS_OFFS (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp.h217 #define REG_DRAM_TRAINING_CS_OFFS 20 macro
Dddr3_hw_training.c665 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
668 reg = (0x1 << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
Dddr3_write_leveling.c86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
509 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw_reg_dimm()
Dddr3_read_leveling.c74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
196 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()