Home
last modified time | relevance | path

Searched refs:REG_DRAM_TRAINING_RL_OFFS (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_sdram.c643 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS); in ddr3_reset_phy_read_fifo()
664 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS); in ddr3_reset_phy_read_fifo()
Dddr3_axp.h214 #define REG_DRAM_TRAINING_RL_OFFS 6 macro
Dddr3_hw_training.c926 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS); in ddr3_training_suspend_resume()
941 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS); in ddr3_training_suspend_resume()
Dddr3_pbs.c675 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS); in ddr3_pbs_rx()
693 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS); in ddr3_pbs_rx()
Dddr3_read_leveling.c69 reg = 1 << REG_DRAM_TRAINING_RL_OFFS; in ddr3_read_leveling_hw()