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Searched refs:REG_PHY_CS_OFFS (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_hw_training.c556 reg |= ((0x4 * cs + mode) << REG_PHY_CS_OFFS); in ddr3_write_pup_reg()
580 reg |= ((0x4 * cs + mode + 1) << REG_PHY_CS_OFFS); in ddr3_write_pup_reg()
602 ((0x4 * cs + mode) << REG_PHY_CS_OFFS); in ddr3_read_pup_reg()
824 reg = (val >> REG_PHY_CS_OFFS) & 0x3F; /*read the phy address */ in ddr3_read_training_results()
Dddr3_axp.h309 #define REG_PHY_CS_OFFS 16 macro
Dddr3_write_leveling.c1355 reg |= (reg_addr << REG_PHY_CS_OFFS); in ddr3_write_ctrl_pup_reg()
Dddr3_pbs.c1516 reg |= ((0x4 * cs + PUP_WL_MODE) << REG_PHY_CS_OFFS); in ddr3_pbs_write_pup_dqs_reg()