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Searched refs:REG_PHY_REGISTRY_FILE_ACCESS_ADDR (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_hw_training.c562 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
564 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
567 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_write_pup_reg()
583 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
585 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
588 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_write_pup_reg()
603 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
606 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
609 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_read_pup_reg()
613 return reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR); /* 0x16A0 */ in ddr3_read_pup_reg()
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Dddr3_init.c795 REG_PHY_REGISTRY_FILE_ACCESS_ADDR) in ddr3_static_training_init()
797 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_static_training_init()
892 REG_PHY_REGISTRY_FILE_ACCESS_ADDR) in ddr3_static_mc_init()
894 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_static_mc_init()
Dddr3_write_leveling.c1357 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_ctrl_pup_reg()
1359 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_ctrl_pup_reg()
1362 reg = (reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR)) & in ddr3_write_ctrl_pup_reg()
Dddr3_axp.h303 #define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0 macro
Dddr3_pbs.c1518 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_pbs_write_pup_dqs_reg()
1520 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) & in ddr3_pbs_write_pup_dqs_reg()