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Searched refs:REG_SDRAM_CONFIG_ADDR (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_dfs.c378 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK); in ddr3_dfs_high_2_low()
381 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
387 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK); in ddr3_dfs_high_2_low()
390 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
663 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK); in ddr3_dfs_high_2_low()
666 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
668 reg = reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK; in ddr3_dfs_high_2_low()
671 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
1038 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & in ddr3_dfs_low_2_high()
1041 tmp = reg_read(REG_SDRAM_CONFIG_ADDR) | in ddr3_dfs_low_2_high()
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Dddr3_init.c84 debug_print_reg(REG_SDRAM_CONFIG_ADDR); in print_dunit_setup()
473 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
475 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
495 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
643 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & in ddr3_init_main()
645 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
661 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
663 reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19)); in ddr3_init_main()
Dddr3_hw_training.c105 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
109 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
114 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
Dddr3_spd.c714 REG_SDRAM_CONFIG_ADDR, REG_SDRAM_CONFIG_ECC_OFFS, 0x1, 0, 0);
758 stat_val = ddr3_get_static_mc_value(REG_SDRAM_CONFIG_ADDR, 0,
776 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
Dddr3_axp.h81 #define REG_SDRAM_CONFIG_ADDR 0x1400 macro
/external/u-boot/arch/arm/mach-mvebu/
Ddram.c176 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
178 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
206 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
208 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
213 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) in ecc_enabled()
224 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) in bus_width()