Searched refs:REG_TRAINING_DEBUG_3_OFFS (Results 1 – 3 of 3) sorted by relevance
515 reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS); in ddr3_init_main()516 reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */ in ddr3_init_main()517 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()518 reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */ in ddr3_init_main()519 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()520 reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()521 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()522 reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_init_main()
662 REG_TRAINING_DEBUG_3_OFFS)); in ddr3_read_leveling_single_cs_rl_mode()718 add = (add >> (phase_min * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_read_leveling_single_cs_rl_mode()1065 REG_TRAINING_DEBUG_3_OFFS); in ddr3_read_leveling_single_cs_window_mode()1191 add = (add >> phase_min * REG_TRAINING_DEBUG_3_OFFS); in ddr3_read_leveling_single_cs_window_mode()
247 #define REG_TRAINING_DEBUG_3_OFFS 3 macro