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Searched refs:REG_TRAINING_WL_1TO1 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp.h319 #define REG_TRAINING_WL_1TO1 0x50 macro
Dddr3_write_leveling.c1193 REG_TRAINING_WL_RATIO_MASK) | REG_TRAINING_WL_1TO1; in ddr3_write_leveling_single_cs()
1239 REG_TRAINING_WL_1TO1; in ddr3_write_leveling_single_cs()