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Searched refs:REG_TRAINING_WL_CS_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp.h315 #define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC macro
Dddr3_write_leveling.c1178 reg = (reg_read(REG_TRAINING_WL_ADDR) & REG_TRAINING_WL_CS_MASK) | cs; in ddr3_write_leveling_single_cs()