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Searched refs:RES (Results 1 – 25 of 174) sorted by relevance

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/external/tcpdump/tests/
D	lldp-infinite-loop-1.out	`29 RES: 0 31 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 32 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 33 Priority: 0, RES: 0, Sel: 0, Protocol ID: 128 34 Priority: 0, RES: 1, Sel: 4, Protocol ID: 3072 35 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 36 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 37 Priority: 4, RES: 0, Sel: 0, Protocol ID: 32962 38 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 39 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/gold/X86/
D	comdat.ll	`6 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 35 ; RES: 1.o,f1,plx{{$}} 36 ; RES: 1.o,v1,px{{$}} 37 ; RES: 1.o,r11,px{{$}} 38 ; RES: 1.o,r12,px{{$}} 39 ; RES: 1.o,a11,px{{$}} 40 ; RES: 1.o,a12,px{{$}} 41 ; RES: 1.o,a13,px{{$}} 42 ; RES: 1.o,a14,px{{$}} 43 ; RES: 1.o,a15,px{{$}} [all …]`
D	emit-llvm.ll	`11 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 100 ; RES: .o,f1,pl{{$}} 101 ; RES: .o,f2,pl{{$}} 102 ; RES: .o,f3,px{{$}} 103 ; RES: .o,f4,p{{$}} 104 ; RES: .o,f5,px{{$}} 105 ; RES: .o,f6,p{{$}} 106 ; RES: .o,f7,px{{$}} 107 ; RES: .o,f8,px{{$}} 108 ; RES: .o,g1,px{{$}} [all …]`
/external/eigen/blas/fortran/
D	complexdots.f	`4 COMPLEX RES local 7 CALL CDOTCW(N,CX,INCX,CY,INCY,RES) 8 CDOTC = RES 15 COMPLEX RES local 18 CALL CDOTUW(N,CX,INCX,CY,INCY,RES) 19 CDOTU = RES 26 DOUBLE COMPLEX RES local 29 CALL ZDOTCW(N,CX,INCX,CY,INCY,RES) 30 ZDOTC = RES 37 DOUBLE COMPLEX RES local [all …]`
/external/llvm/test/CodeGen/Mips/msa/
D	elm_copy.ll	31 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES) 32 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES) 33 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 54 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES) 55 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES) 56 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 77 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES) 78 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES) 79 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 103 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES) [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
D	elm_copy.ll	31 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES) 32 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES) 33 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 54 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES) 55 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES) 56 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 77 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES) 78 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES) 79 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 103 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES) [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
D	select-atomicrmw.mir	33 ; CHECK: [[RES:%[0-9]+]]:gpr64 = SWPX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr) 34 ; CHECK: $x0 = COPY [[RES]] 52 … ; CHECK: [[RES:%[0-9]+]]:gpr64 = LDADDX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr) 53 ; CHECK: $x0 = COPY [[RES]] 71 … ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr) 72 ; CHECK: $w0 = COPY [[RES]] 91 … ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr) 92 ; CHECK: $w0 = COPY [[RES]] 112 … ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDCLRAW [[CST2]], [[COPY]] :: (load store acquire 4 on %ir.addr) 113 ; CHECK: $w0 = COPY [[RES]] [all …]
D	legalize-atomicrmw.mir	23 …; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 1… 24 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] 43 …; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic … 44 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] 62 …; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 4… 63 ; CHECK: $w0 = COPY [[RES]] 79 …; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 8… 80 ; CHECK: $x0 = COPY [[RES]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/LTO/Resolution/X86/
D	alias-alias.ll	`5 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 14 ; RES: 1.o{{$}} 15 ; RES-NEXT: {{^}}-r={{.}}1.o,c,p{{$}} 16 ; RES-NEXT: {{^}}-r={{.}}1.o,a,p{{$}} 17 ; RES-NEXT: {{^}}-r={{.}}1.o,b,{{$}} 18 ; RES-NEXT: 2.o{{$}} 19 ; RES-NEXT: {{^}}-r={{.}}2.o,a,{{$}} 20 ; RES-NEXT: {{^}}-r={{.*}}2.o,d,px{{$}}`
D	alias.ll	`5 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 12 ; RES: 2.o{{$}} 13 ; RES: {{^}}-r={{.}}2.o,a,px{{$}} 14 ; RES: 1.o{{$}} 15 ; RES: {{^}}-r={{.}}1.o,b,px{{$}} 16 ; RES: {{^}}-r={{.*}}1.o,a,{{$}}`
/external/llvm/test/CodeGen/Mips/Fast-ISel/
D	logopm.ll	`42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 43 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 64 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 87 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 88 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 113 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 114 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 133 ; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1 134 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) [all …]`
D	shftopm.ll	`28 ; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]] 29 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 45 ; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5 46 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 66 ; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]] 67 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 82 ; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4 83 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 102 ; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]] 103 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/
D	logopm.ll	`42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 43 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 64 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 87 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 88 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 113 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 114 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 133 ; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1 134 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) [all …]`
D	shftopm.ll	`28 ; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]] 29 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 45 ; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5 46 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 66 ; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]] 67 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 82 ; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4 83 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 102 ; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]] 103 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/CodeGenPrepare/X86/
D	x86-shuffle-sink.ll	17 ; CHECK-NEXT: [[RES:%.]] = shl <16 x i8> [[LHS:%.]], [[MASK]] 18 ; CHECK-NEXT: ret <16 x i8> [[RES]] 39 ; CHECK-SSE2-NEXT: [[RES:%.]] = shl <8 x i16> [[LHS:%.]], [[TMP1]] 40 ; CHECK-SSE2-NEXT: ret <8 x i16> [[RES]] 48 ; CHECK-XOP-NEXT: [[RES:%.]] = shl <8 x i16> [[LHS:%.]], [[MASK]] 49 ; CHECK-XOP-NEXT: ret <8 x i16> [[RES]] 58 ; CHECK-AVX2-NEXT: [[RES:%.]] = shl <8 x i16> [[LHS:%.]], [[TMP1]] 59 ; CHECK-AVX2-NEXT: ret <8 x i16> [[RES]] 67 ; CHECK-AVX512BW-NEXT: [[RES:%.]] = shl <8 x i16> [[LHS:%.]], [[MASK]] 68 ; CHECK-AVX512BW-NEXT: ret <8 x i16> [[RES]] [all …]
/external/llvm/test/CodeGen/ARM/
D	vector-promotion.ll	128 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7 131 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 133 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 147 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7 150 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 152 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 166 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7 169 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 171 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 185 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7 [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D	vector-promotion.ll	128 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7 131 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 133 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 147 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7 150 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 152 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 166 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7 169 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 171 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 185 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7 [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
D	dagcombine-setcc-select.ll	13 ; GCN: v_cndmask_b32_e{{32\|64}} [[RES:v[0-9]+]], [[TWO]], [[FOUR]], [[CC]] 14 ; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}} 34 ; GCN: v_cndmask_b32_e{{32\|64}} [[RES:v[0-9]+]], [[FOUR]], [[TWO]], [[CC]] 35 ; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}} 55 ; GCN: v_cndmask_b32_e{{32\|64}} [[RES:v[0-9]+]], [[FOUR]], [[TWO]], [[CC]] 56 ; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}} 76 ; GCN: v_cndmask_b32_e{{32\|64}} [[RES:v[0-9]+]], [[TWO]], [[FOUR]], [[CC]] 77 ; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}} 95 ; GCN: v_cndmask_b32_e{{32\|64}} [[RES:v[0-9]+]], [[TWO]], [[FOUR]], [[CC2]] 96 ; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
D	fp-mul-12.ll	`10 ; CHECK: wfmaxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]] 11 ; CHECK: vst [[RES]], 0(%r5) 26 ; CHECK: wfmsxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]] 27 ; CHECK: vst [[RES]], 0(%r5) 43 ; CHECK: wfnmaxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]] 44 ; CHECK: vst [[RES]], 0(%r5) 60 ; CHECK: wfnmsxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]] 61 ; CHECK: vst [[RES]], 0(%r5)`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D	add-sitofp.ll	23 ; CHECK-NEXT: [[RES:%.]] = sitofp i32 [[ADDCONV]] to double 24 ; CHECK-NEXT: ret double [[RES]] 37 ; CHECK-NEXT: [[RES:%.]] = fadd float [[A_AND_FP]], 1.000000e+00 38 ; CHECK-NEXT: ret float [[RES]] 52 ; CHECK-NEXT: [[RES:%.]] = sitofp i32 [[ADDCONV]] to double 53 ; CHECK-NEXT: ret double [[RES]] 72 ; CHECK-NEXT: [[RES:%.]] = fadd float [[A_AND_FP]], [[B_AND_FP]] 73 ; CHECK-NEXT: ret float [[RES]] 109 ; CHECK-NEXT: [[RES:%.*]] = sitofp <4 x i32> [[ADDCONV]] to <4 x double> 110 ; CHECK-NEXT: ret <4 x double> [[RES]] [all …]
/external/u-boot/scripts/
D	Lindent	3 RES=`indent --version` 4 V1=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f1` 5 V2=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f2` 6 V3=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f3`
/external/selinux/scripts/
D	Lindent	3 RES=`indent --version` 4 V1=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f1` 5 V2=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f2` 6 V3=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f3`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D	codegen-prepare-extload.ll	37 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2 40 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 41 ; OPTALL: store i32 [[RES]], i32* %q 63 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2 65 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32 66 ; OPTALL: store i32 [[RES]], i32* %q 97 ; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]] 100 ; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 103 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 105 ; OPTALL: store i32 [[RES]], i32* %q [all …]
/external/llvm/test/CodeGen/X86/
D	codegen-prepare-extload.ll	37 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2 40 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 41 ; OPTALL: store i32 [[RES]], i32* %q 63 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2 65 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32 66 ; OPTALL: store i32 [[RES]], i32* %q 97 ; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]] 100 ; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 103 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 105 ; OPTALL: store i32 [[RES]], i32* %q [all …]
/external/llvm/test/CodeGen/AMDGPU/
D	fma.ll	13 ; EG: MEM_RAT_{{.}} STORE_{{.}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 14 ; EG: FMA {{\? }}[[RES]] 29 ; EG: MEM_RAT_{{.}} STORE_{{.}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}}, 30 ; EG-DAG: FMA {{\? }}[[RES]].[[CHLO]] 31 ; EG-DAG: FMA {{\? }}[[RES]].[[CHHI]] 48 ; EG: MEM_RAT_{{.}} STORE_{{.}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}}, 49 ; EG-DAG: FMA {{\? }}[[RES]].X 50 ; EG-DAG: FMA {{\? }}[[RES]].Y 51 ; EG-DAG: FMA {{\? }}[[RES]].Z 52 ; EG-DAG: FMA {{\? }}[[RES]].W

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