/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 4121 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4123 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4126 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4128 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4132 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4135 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4148 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4150 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4152 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4157 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), [all …]
|
D | ARMInstrThumb2.td | 561 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 563 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 2819 def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2820 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>; 2821 def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2822 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>; 2823 def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2824 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>; 2825 def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2826 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>; [all …]
|
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenMCPseudoLowering.inc | 139 // Operand: RHi 239 // Operand: RHi
|
D | ARMGenDAGISel.inc | 29232 /* 63937*/ OPC_RecordChild3, // #3 = $RHi 29239 …:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$RHi) - Complexity = 3 29240 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) 29247 …:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$RHi) - Complexity = 3 29248 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) 29254 /* 63990*/ OPC_RecordChild3, // #3 = $RHi 29261 …:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$RHi) - Complexity = 3 29262 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) 29269 …:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$RHi) - Complexity = 3 29270 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) [all …]
|
/external/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 3941 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3943 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3945 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3947 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3950 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 3953 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]> { 3965 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 3967 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3969 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3973 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), [all …]
|
D | ARMInstrThumb2.td | 2586 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2588 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">; 2592 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2594 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">; 2598 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2600 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
|
/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 19374 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi); in LowerMUL() local 19376 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT)); in LowerMUL() 19377 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMUL() 19554 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi); in LowerMULH() local 19556 RHi = DAG.getNode(ISD::SRL, dl, ExVT, RHi, DAG.getConstant(8, dl, ExVT)); in LowerMULH() 19557 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMULH() 20286 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R); in LowerShift() local 20290 RHi = DAG.getBitcast(ExtVT, RHi); in LowerShift() 20295 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi, in LowerShift() 20298 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift() [all …]
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 22617 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi); in LowerMUL() local 22619 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT)); in LowerMUL() 22620 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMUL() 22831 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi); in LowerMULH() local 22833 RHi = DAG.getNode(ISD::SRL, dl, ExVT, RHi, DAG.getConstant(8, dl, ExVT)); in LowerMULH() 22834 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMULH() 23692 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R); in LowerShift() local 23696 RHi = DAG.getBitcast(ExtVT, RHi); in LowerShift() 23701 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi, in LowerShift() 23704 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi); in LowerShift() [all …]
|
/external/toolchain-utils/android_bench_suite/panorama_input/ |
D | test_008.ppm | 9178 …dRXRBTO>YSC]WF_WFkbRldVkbTnfXg_Q^VH_WIYQCaYKQI;SK=YQC]TFPF<^TJlbXof[aXMTKA[RHi`Vpe[pe[oaVzl`vh]�vk…
|