Searched refs:RISCVInstrInfo (Results 1 – 9 of 9) sorted by relevance
32 RISCVInstrInfo::RISCVInstrInfo() in RISCVInstrInfo() function in RISCVInstrInfo35 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()61 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()84 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()109 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, in storeRegToStackSlot()136 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, in loadRegFromStackSlot()160 void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB, in movImm32()213 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()281 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, in removeBranch()315 unsigned RISCVInstrInfo::insertBranch( in insertBranch()[all …]
68 include "RISCVInstrInfo.td"82 def RISCVInstrInfo : InstrInfo {96 let InstructionSet = RISCVInstrInfo;
43 RISCVInstrInfo InstrInfo;65 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
25 class RISCVInstrInfo : public RISCVGenInstrInfo {28 RISCVInstrInfo();
19 RISCVInstrInfo.cpp
76 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); in eliminateFrameIndex()
59 const RISCVInstrInfo *TII = STI.getInstrInfo(); in adjustReg()
1 //===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===//
443 ; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot444 ; and RISCVInstrInfo::loadRegFromStackSlot