Searched refs:RLLG (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-08.ll | 5 ; Check the low end of the RLLG range.
16 ; Check the high end of the defined RLLG range.
|
| D | rot-02.ll | 54 ; Test removal of AND mask from RLLG.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | shift-08.ll | 5 ; Check the low end of the RLLG range.
16 ; Check the high end of the defined RLLG range.
|
| D | rot-02.ll | 54 ; Test removal of AND mask from RLLG.
|
| /external/v8/src/s390/ |
| D | simulator-s390.h | 1085 EVALUATE(RLLG);
|
| D | constants-s390.h | 164 V(rllg, RLLG, 0xEB1C) /* type = RSY_A ROTATE LEFT SINGLE LOGICAL (64) */ \
|
| D | simulator-s390.cc | 1372 EvalTable[RLLG] = &Simulator::Evaluate_RLLG; in EvalTableInit()
8786 EVALUATE(RLLG) { in EVALUATE() argument
8787 DCHECK_OPCODE(RLLG); in EVALUATE()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1230 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
1747 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1380 def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;
2187 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>;
|
| /external/capstone/arch/SystemZ/ |
| D | SystemZGenAsmWriter.inc | 814 977278127U, // RLLG
|
| D | SystemZGenDisassemblerTables.inc | 1193 /* 1438 */ MCD_OPC_Decode, 153, 6, 119, // Opcode: RLLG
|