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Searched refs:RL_PHY_REG (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_leveling.c307 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_read_leveling()
716 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_per_bit_read_leveling()
763 ddr3_tip_write_cs_result(dev_num, RL_PHY_REG(0)); in ddr3_tip_dynamic_per_bit_read_leveling()
1786 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1965 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
Dmv_ddr_regs.h399 #define RL_PHY_REG(cs) (RL_PHY_BASE + (cs) * 0x4) macro
Dddr3_training_hw_algo.c78 RL_PHY_REG(cs_num), in ddr3_tip_write_additional_odt_setting()
Dddr3_training_ip_engine.c1478 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1500 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
Dddr3_debug.c614 RL_PHY_REG(csindex), in ddr3_tip_print_stability_log()
1480 reg = (direction == 0) ? WL_PHY_REG(cs) : RL_PHY_REG(cs); in ddr3_tip_run_leveling_sweep_test()
Dddr3_training.c2024 RL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()