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Searched refs:ROR (Results 1 – 25 of 152) sorted by relevance

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/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-operand-rn-ror-amount-a32.cc102 {{vc, r2, r5, ROR, 0}, false, al, "vc r2 r5 ROR 0", "vc_r2_r5_ROR_0"},
103 {{eq, r5, r7, ROR, 0}, false, al, "eq r5 r7 ROR 0", "eq_r5_r7_ROR_0"},
104 {{ge, r3, r2, ROR, 8}, false, al, "ge r3 r2 ROR 8", "ge_r3_r2_ROR_8"},
105 {{cc, r11, r3, ROR, 16}, false, al, "cc r11 r3 ROR 16", "cc_r11_r3_ROR_16"},
106 {{cs, r13, r6, ROR, 0}, false, al, "cs r13 r6 ROR 0", "cs_r13_r6_ROR_0"},
107 {{al, r6, r7, ROR, 16}, false, al, "al r6 r7 ROR 16", "al_r6_r7_ROR_16"},
108 {{le, r12, r12, ROR, 0}, false, al, "le r12 r12 ROR 0", "le_r12_r12_ROR_0"},
109 {{mi, r4, r5, ROR, 16}, false, al, "mi r4 r5 ROR 16", "mi_r4_r5_ROR_16"},
110 {{pl, r9, r2, ROR, 16}, false, al, "pl r9 r2 ROR 16", "pl_r9_r2_ROR_16"},
111 {{vs, r5, r11, ROR, 8}, false, al, "vs r5 r11 ROR 8", "vs_r5_r11_ROR_8"},
[all …]
Dtest-assembler-cond-rd-operand-rn-ror-amount-t32.cc102 {{al, r0, r0, ROR, 0}, false, al, "al r0 r0 ROR 0", "al_r0_r0_ROR_0"},
103 {{al, r0, r0, ROR, 8}, false, al, "al r0 r0 ROR 8", "al_r0_r0_ROR_8"},
104 {{al, r0, r0, ROR, 16}, false, al, "al r0 r0 ROR 16", "al_r0_r0_ROR_16"},
105 {{al, r0, r0, ROR, 24}, false, al, "al r0 r0 ROR 24", "al_r0_r0_ROR_24"},
106 {{al, r0, r1, ROR, 0}, false, al, "al r0 r1 ROR 0", "al_r0_r1_ROR_0"},
107 {{al, r0, r1, ROR, 8}, false, al, "al r0 r1 ROR 8", "al_r0_r1_ROR_8"},
108 {{al, r0, r1, ROR, 16}, false, al, "al r0 r1 ROR 16", "al_r0_r1_ROR_16"},
109 {{al, r0, r1, ROR, 24}, false, al, "al r0 r1 ROR 24", "al_r0_r1_ROR_24"},
110 {{al, r0, r2, ROR, 0}, false, al, "al r0 r2 ROR 0", "al_r0_r2_ROR_0"},
111 {{al, r0, r2, ROR, 8}, false, al, "al r0 r2 ROR 8", "al_r0_r2_ROR_8"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc102 const TestData kTests[] = {{{ls, r3, r3, r13, ROR, 0},
107 {{cs, r2, r7, r1, ROR, 16},
112 {{mi, r13, r0, r2, ROR, 8},
117 {{lt, r0, r6, r1, ROR, 8},
122 {{al, r6, r4, r8, ROR, 16},
127 {{gt, r1, r7, r10, ROR, 16},
132 {{cc, r12, r9, r11, ROR, 16},
137 {{mi, r6, r8, r13, ROR, 24},
142 {{mi, r9, r1, r6, ROR, 16},
147 {{le, r8, r9, r14, ROR, 8},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc102 const TestData kTests[] = {{{al, r4, r0, r8, ROR, 16},
107 {{al, r14, r13, r12, ROR, 24},
112 {{al, r9, r10, r5, ROR, 16},
117 {{al, r11, r13, r14, ROR, 8},
122 {{al, r3, r12, r11, ROR, 16},
127 {{al, r0, r11, r6, ROR, 24},
132 {{al, r1, r9, r13, ROR, 16},
137 {{al, r14, r4, r11, ROR, 16},
142 {{al, r2, r13, r5, ROR, 16},
147 {{al, r9, r1, r0, ROR, 24},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc104 {{vc, r5, r5, ROR, 10}, false, al, "vc r5 r5 ROR 10", "vc_r5_r5_ROR_10"},
105 {{ne, r3, r4, ROR, 17}, false, al, "ne r3 r4 ROR 17", "ne_r3_r4_ROR_17"},
106 {{cs, r9, r10, ROR, 16}, false, al, "cs r9 r10 ROR 16", "cs_r9_r10_ROR_16"},
107 {{lt, r0, r2, ROR, 29}, false, al, "lt r0 r2 ROR 29", "lt_r0_r2_ROR_29"},
108 {{al, r11, r2, ROR, 23}, false, al, "al r11 r2 ROR 23", "al_r11_r2_ROR_23"},
110 {{eq, r5, r3, ROR, 21}, false, al, "eq r5 r3 ROR 21", "eq_r5_r3_ROR_21"},
111 {{pl, r2, r10, ROR, 13}, false, al, "pl r2 r10 ROR 13", "pl_r2_r10_ROR_13"},
113 {{mi, r11, r10, ROR, 31},
120 {{eq, r10, r11, ROR, 7}, false, al, "eq r10 r11 ROR 7", "eq_r10_r11_ROR_7"},
121 {{vs, r4, r3, ROR, 18}, false, al, "vs r4 r3 ROR 18", "vs_r4_r3_ROR_18"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc104 {{al, r14, r8, ROR, 21}, false, al, "al r14 r8 ROR 21", "al_r14_r8_ROR_21"},
105 {{al, r5, r13, ROR, 4}, false, al, "al r5 r13 ROR 4", "al_r5_r13_ROR_4"},
106 {{al, r0, r3, ROR, 4}, false, al, "al r0 r3 ROR 4", "al_r0_r3_ROR_4"},
107 {{al, r3, r14, ROR, 7}, false, al, "al r3 r14 ROR 7", "al_r3_r14_ROR_7"},
111 {{al, r0, r9, ROR, 17}, false, al, "al r0 r9 ROR 17", "al_r0_r9_ROR_17"},
112 {{al, r11, r3, ROR, 31}, false, al, "al r11 r3 ROR 31", "al_r11_r3_ROR_31"},
113 {{al, r8, r8, ROR, 20}, false, al, "al r8 r8 ROR 20", "al_r8_r8_ROR_20"},
119 {{al, r1, r3, ROR, 27}, false, al, "al r1 r3 ROR 27", "al_r1_r3_ROR_27"},
120 {{al, r9, r10, ROR, 5}, false, al, "al r9 r10 ROR 5", "al_r9_r10_ROR_5"},
121 {{al, r3, r11, ROR, 25}, false, al, "al r3 r11 ROR 25", "al_r3_r11_ROR_25"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc121 {{al, r7, r8, r10, ROR, 21},
126 {{al, r5, r5, r3, ROR, 12},
136 {{al, r9, r10, r11, ROR, 2},
151 {{al, r2, r11, r1, ROR, 9},
161 {{al, r6, r13, r3, ROR, 1},
191 {{al, r3, r1, r6, ROR, 3},
201 {{al, r2, r0, r6, ROR, 3},
206 {{al, r7, r10, r10, ROR, 19},
226 {{al, r10, r3, r6, ROR, 1},
231 {{al, r6, r14, r2, ROR, 13},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc136 {{cc, r10, r5, r1, ROR, 10},
141 {{ge, r3, r14, r7, ROR, 7},
171 {{cs, r12, r3, r0, ROR, 20},
176 {{vs, r1, r6, r9, ROR, 14},
186 {{vc, r14, r13, r10, ROR, 7},
191 {{ge, r12, r0, r6, ROR, 4},
201 {{gt, r1, r4, r7, ROR, 10},
206 {{ne, r8, r11, r14, ROR, 19},
211 {{vc, r4, r11, r5, ROR, 15},
221 {{pl, r13, r12, r9, ROR, 25},
[all …]
Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc602 {{al, r0, r2, plus, r14, ROR, 9, Offset},
617 {{al, r0, r4, plus, r12, ROR, 13, Offset},
627 {{al, r0, r7, plus, r0, ROR, 25, Offset},
647 {{al, r0, r7, plus, r12, ROR, 11, Offset},
677 {{al, r0, r8, minus, r7, ROR, 30, Offset},
682 {{al, r0, r4, minus, r11, ROR, 19, Offset},
687 {{al, r0, r9, minus, r11, ROR, 23, Offset},
692 {{al, r0, r12, plus, r12, ROR, 28, Offset},
697 {{al, r0, r9, plus, r12, ROR, 25, Offset},
707 {{al, r0, r6, minus, r12, ROR, 24, Offset},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-a32.cc110 {{ge, r11, r13, ROR, r2},
121 {{eq, r3, r0, ROR, r11}, false, al, "eq r3 r0 ROR r11", "eq_r3_r0_ROR_r11"},
127 {{ge, r14, r6, ROR, r13},
138 {{ge, r4, r6, ROR, r7}, false, al, "ge r4 r6 ROR r7", "ge_r4_r6_ROR_r7"},
160 {{hi, r9, r11, ROR, r13},
173 {{lt, r5, r1, ROR, r5}, false, al, "lt r5 r1 ROR r5", "lt_r5_r1_ROR_r5"},
174 {{eq, r5, r12, ROR, r0}, false, al, "eq r5 r12 ROR r0", "eq_r5_r12_ROR_r0"},
184 {{al, r12, r10, ROR, r0},
190 {{cc, r14, r14, ROR, r0},
195 {{ge, r2, r14, ROR, r9}, false, al, "ge r2 r14 ROR r9", "ge_r2_r14_ROR_r9"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32.cc111 {{al, r12, r3, ROR, r5}, false, al, "al r12 r3 ROR r5", "al_r12_r3_ROR_r5"},
133 {{al, r12, r11, ROR, r7},
143 {{al, r11, r7, ROR, r0}, false, al, "al r11 r7 ROR r0", "al_r11_r7_ROR_r0"},
144 {{al, r6, r13, ROR, r2}, false, al, "al r6 r13 ROR r2", "al_r6_r13_ROR_r2"},
155 {{al, r4, r2, ROR, r3}, false, al, "al r4 r2 ROR r3", "al_r4_r2_ROR_r3"},
156 {{al, r10, r6, ROR, r11},
161 {{al, r5, r8, ROR, r7}, false, al, "al r5 r8 ROR r7", "al_r5_r8_ROR_r7"},
168 {{al, r4, r1, ROR, r10}, false, al, "al r4 r1 ROR r10", "al_r4_r1_ROR_r10"},
213 {{al, r2, r9, ROR, r6}, false, al, "al r2 r9 ROR r6", "al_r2_r9_ROR_r6"},
217 {{al, r1, r7, ROR, r0}, false, al, "al r1 r7 ROR r0", "al_r1_r7_ROR_r0"},
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc348 {{al, r4, r12, plus, r9, ROR, 12, Offset},
378 {{al, r0, r11, plus, r4, ROR, 2, Offset},
388 {{al, r2, r11, plus, r9, ROR, 29, Offset},
408 {{al, r5, r1, plus, r3, ROR, 19, Offset},
428 {{al, r7, r14, plus, r0, ROR, 17, Offset},
438 {{al, r14, r0, plus, r2, ROR, 27, Offset},
453 {{al, r14, r4, plus, r6, ROR, 5, Offset},
463 {{al, r14, r8, plus, r9, ROR, 13, Offset},
478 {{al, r10, r8, plus, r9, ROR, 25, Offset},
488 {{al, r7, r5, plus, r10, ROR, 24, Offset},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc99 {{pl, r3, r3, ROR, r3}, true, pl, "pl r3 r3 ROR r3", "pl_r3_r3_ROR_r3"},
100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"},
104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
116 {{eq, r5, r5, ROR, r2}, true, eq, "eq r5 r5 ROR r2", "eq_r5_r5_ROR_r2"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"},
124 {{ne, r3, r3, ROR, r4}, true, ne, "ne r3 r3 ROR r4", "ne_r3_r3_ROR_r4"},
133 {{eq, r4, r4, ROR, r4}, true, eq, "eq r4 r4 ROR r4", "eq_r4_r4_ROR_r4"},
134 {{vc, r5, r5, ROR, r3}, true, vc, "vc r5 r5 ROR r3", "vc_r5_r5_ROR_r3"},
137 {{lt, r4, r4, ROR, r3}, true, lt, "lt r4 r4 ROR r3", "lt_r4_r4_ROR_r3"},
140 {{ne, r6, r6, ROR, r6}, true, ne, "ne r6 r6 ROR r6", "ne_r6_r6_ROR_r6"},
[all …]
Dtest-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc121 {{eq, r9, r15, r1, ROR, r1},
127 {{ge, r15, r5, r13, ROR, r5},
145 {{mi, r15, r3, r8, ROR, r6},
160 {{vc, r0, r8, r5, ROR, r15},
169 {{le, r15, r15, r3, ROR, r2},
172 {{pl, r15, r9, r14, ROR, r13},
193 {{hi, r15, r4, r4, ROR, r0},
196 {{ge, r8, r14, r8, ROR, r15},
199 {{cs, r11, r6, r15, ROR, r13},
226 {{vs, r15, r2, r15, ROR, r6},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc121 {{cc, r11, r4, r13, ROR, r8},
126 {{al, r13, r11, r3, ROR, r4},
136 {{vs, r12, r0, r8, ROR, r13},
156 {{mi, r3, r13, r0, ROR, r11},
166 {{le, r12, r8, r14, ROR, r1},
176 {{le, r11, r13, r3, ROR, r6},
206 {{ls, r13, r5, r11, ROR, r8},
226 {{ne, r14, r6, r12, ROR, r0},
236 {{lt, r10, r13, r7, ROR, r8},
291 {{mi, r3, r9, r13, ROR, r10},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc120 {{al, r0, r0, ROR, r0}, false, al, "al r0 r0 ROR r0", "al_r0_r0_ROR_r0"},
121 {{al, r0, r0, ROR, r1}, false, al, "al r0 r0 ROR r1", "al_r0_r0_ROR_r1"},
122 {{al, r0, r0, ROR, r2}, false, al, "al r0 r0 ROR r2", "al_r0_r0_ROR_r2"},
123 {{al, r0, r0, ROR, r3}, false, al, "al r0 r0 ROR r3", "al_r0_r0_ROR_r3"},
124 {{al, r0, r0, ROR, r4}, false, al, "al r0 r0 ROR r4", "al_r0_r0_ROR_r4"},
125 {{al, r0, r0, ROR, r5}, false, al, "al r0 r0 ROR r5", "al_r0_r0_ROR_r5"},
126 {{al, r0, r0, ROR, r6}, false, al, "al r0 r0 ROR r6", "al_r0_r0_ROR_r6"},
127 {{al, r0, r0, ROR, r7}, false, al, "al r0 r0 ROR r7", "al_r0_r0_ROR_r7"},
152 {{al, r1, r1, ROR, r0}, false, al, "al r1 r1 ROR r0", "al_r1_r1_ROR_r0"},
153 {{al, r1, r1, ROR, r1}, false, al, "al r1 r1 ROR r1", "al_r1_r1_ROR_r1"},
[all …]
Dtest-simulator-cond-rd-operand-rn-ror-amount-a32.cc321 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0},
326 {{ne, r0, r0, ROR, 0},
331 {{cs, r0, r0, ROR, 0},
336 {{cc, r0, r0, ROR, 0},
341 {{mi, r0, r0, ROR, 0},
346 {{pl, r0, r0, ROR, 0},
351 {{vs, r0, r0, ROR, 0},
356 {{vc, r0, r0, ROR, 0},
361 {{hi, r0, r0, ROR, 0},
366 {{ls, r0, r0, ROR, 0},
[all …]
Dtest-simulator-cond-rd-operand-rn-ror-amount-t32.cc321 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0},
326 {{ne, r0, r0, ROR, 0},
331 {{cs, r0, r0, ROR, 0},
336 {{cc, r0, r0, ROR, 0},
341 {{mi, r0, r0, ROR, 0},
346 {{pl, r0, r0, ROR, 0},
351 {{vs, r0, r0, ROR, 0},
356 {{vc, r0, r0, ROR, 0},
361 {{hi, r0, r0, ROR, 0},
366 {{ls, r0, r0, ROR, 0},
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc823 const TestLoopData kTests[] = {{{eq, r0, r0, r0, ROR, 0},
828 {{ne, r0, r0, r0, ROR, 0},
833 {{cs, r0, r0, r0, ROR, 0},
838 {{cc, r0, r0, r0, ROR, 0},
843 {{mi, r0, r0, r0, ROR, 0},
848 {{pl, r0, r0, r0, ROR, 0},
853 {{vs, r0, r0, r0, ROR, 0},
858 {{vc, r0, r0, r0, ROR, 0},
863 {{hi, r0, r0, r0, ROR, 0},
868 {{ls, r0, r0, r0, ROR, 0},
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc823 const TestLoopData kTests[] = {{{eq, r0, r0, r0, ROR, 0},
828 {{ne, r0, r0, r0, ROR, 0},
833 {{cs, r0, r0, r0, ROR, 0},
838 {{cc, r0, r0, r0, ROR, 0},
843 {{mi, r0, r0, r0, ROR, 0},
848 {{pl, r0, r0, r0, ROR, 0},
853 {{vs, r0, r0, r0, ROR, 0},
858 {{vc, r0, r0, r0, ROR, 0},
863 {{hi, r0, r0, r0, ROR, 0},
868 {{ls, r0, r0, r0, ROR, 0},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc673 {{al, r0, r1, ROR, 1},
678 {{al, r0, r1, ROR, 2},
683 {{al, r0, r1, ROR, 3},
688 {{al, r0, r1, ROR, 4},
693 {{al, r0, r1, ROR, 5},
698 {{al, r0, r1, ROR, 6},
703 {{al, r0, r1, ROR, 7},
708 {{al, r0, r1, ROR, 8},
713 {{al, r0, r1, ROR, 9},
718 {{al, r0, r1, ROR, 10},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc673 {{al, r0, r0, ROR, 1},
678 {{al, r0, r0, ROR, 2},
683 {{al, r0, r0, ROR, 3},
688 {{al, r0, r0, ROR, 4},
693 {{al, r0, r0, ROR, 5},
698 {{al, r0, r0, ROR, 6},
703 {{al, r0, r0, ROR, 7},
708 {{al, r0, r0, ROR, 8},
713 {{al, r0, r0, ROR, 9},
718 {{al, r0, r0, ROR, 10},
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc1217 {{al, r0, r1, r2, ROR, 1},
1222 {{al, r0, r1, r2, ROR, 2},
1227 {{al, r0, r1, r2, ROR, 3},
1232 {{al, r0, r1, r2, ROR, 4},
1237 {{al, r0, r1, r2, ROR, 5},
1242 {{al, r0, r1, r2, ROR, 6},
1247 {{al, r0, r1, r2, ROR, 7},
1252 {{al, r0, r1, r2, ROR, 8},
1257 {{al, r0, r1, r2, ROR, 9},
1262 {{al, r0, r1, r2, ROR, 10},
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc1217 {{al, r0, r0, r1, ROR, 1},
1222 {{al, r0, r0, r1, ROR, 2},
1227 {{al, r0, r0, r1, ROR, 3},
1232 {{al, r0, r0, r1, ROR, 4},
1237 {{al, r0, r0, r1, ROR, 5},
1242 {{al, r0, r0, r1, ROR, 6},
1247 {{al, r0, r0, r1, ROR, 7},
1252 {{al, r0, r0, r1, ROR, 8},
1257 {{al, r0, r0, r1, ROR, 9},
1262 {{al, r0, r0, r1, ROR, 10},
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-operand-rn-ror-amount-a32.json28 // MNEMONIC{<c>} <Rd>, <Rn>, ROR #<amount>
32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
33 "Sxtb16", // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
34 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
35 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
36 "Uxtb16", // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
37 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1

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