Searched refs:RORV (Results 1 – 12 of 12) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 169 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64InstrInfo.td | 705 defm RORV : Shift<0b11, "ror", rotr>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 171 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64SchedFalkorDetails.td | 1232 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(LSLV|LSRV|ASRV|RORV)(W|X)r$")>;
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| D | AArch64InstrInfo.td | 904 defm RORV : Shift<0b11, "ror", rotr>;
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1062 RORV = RORV_w, enumerator
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| D | disasm-arm64.cc | 606 FORMAT(RORV, "ror"); in VisitDataProcessing2Source()
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| D | assembler-arm64.cc | 1298 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1234 RORV = RORV_w, enumerator
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| D | disasm-aarch64.cc | 777 FORMAT(RORV, "ror"); in VisitDataProcessing2Source()
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| D | assembler-aarch64.cc | 655 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 969 ### RORV ### subsection
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