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Searched refs:RX0 (Results 1 – 8 of 8) sorted by relevance

/external/clang/test/Layout/
Dms-x86-alias-avoidance-padding.cpp306 struct RX0 : RB, RA {}; struct
316 struct RZ0 : RX0, RY {};
/external/u-boot/drivers/pinctrl/renesas/
Dpfc-r8a77970.c214 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_…
675 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
Dpfc-r8a7795.c167 #define GPSR5_1 F_(RX0, IP11_31_28)
312 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_…
1135 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
Dpfc-r8a7796.c173 #define GPSR5_1 F_(RX0, IP11_31_28)
318 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_…
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
Dpfc-r8a7792.c452 PINMUX_SINGLE(RX0),
Dpfc-r8a7790.c1591 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
Dpfc-r8a7791.c910 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Df16x2-instructions.ll1308 ; CHECK: mov.b32 {[[RX0:%h[0-9]+]], [[RX1:%h[0-9]+]]}, [[R]]
1309 ; CHECK-DAG: cvt.f32.f16 [[XR0:%f[0-9]+]], [[RX0]];