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Searched refs:RZ (Results 1 – 25 of 211) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Dfastcc.ll3 …linux-gnu -disable-fp-elim -tailcallopt -aarch64-redzone | FileCheck %s -check-prefix CHECK-TAIL-RZ
168 ; CHECK-TAIL-RZ-LABEL: func_stack32_leaf:
169 ; CHECK-TAIL-RZ: str x20, [sp, #-16]!
170 ; CHECK-TAIL-RZ-NOT: sub sp, sp
171 ; CHECK-TAIL-RZ: nop
172 ; CHECK-TAIL-RZ-NEXT: //NO_APP
173 ; CHECK-TAIL-RZ-NEXT: ldr x20, [sp], #16
174 ; CHECK-TAIL-RZ-NEXT: add sp, sp, #32
175 ; CHECK-TAIL-RZ-NEXT: ret
202 ; CHECK-TAIL-RZ-LABEL: func_stack32_leaf_local:
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dfastcc.ll3 …linux-gnu -disable-fp-elim -tailcallopt -aarch64-redzone | FileCheck %s -check-prefix CHECK-TAIL-RZ
174 ; CHECK-TAIL-RZ-LABEL: func_stack32_leaf:
175 ; CHECK-TAIL-RZ: str x20, [sp, #-16]!
176 ; CHECK-TAIL-RZ-NOT: sub sp, sp
177 ; CHECK-TAIL-RZ: nop
178 ; CHECK-TAIL-RZ-NEXT: //NO_APP
179 ; CHECK-TAIL-RZ-NEXT: ldr x20, [sp], #16
180 ; CHECK-TAIL-RZ-NEXT: add sp, sp, #32
181 ; CHECK-TAIL-RZ-NEXT: ret
208 ; CHECK-TAIL-RZ-LABEL: func_stack32_leaf_local:
[all …]
/external/compiler-rt/test/asan/TestCases/
Dalloca_vla_interact.cc18 #define RZ 32 macro
26 top = alloca1 - RZ; in foo()
35 bot = (char *)alloca(i) - RZ; in foo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTX.h128 RZ, enumerator
/external/llvm/lib/Target/NVPTX/
DNVPTX.h130 RZ, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dexpand-isel-7.mir1 # This file tests the scenario: ISEL RX, RY, RZ, CR (X != 0 && Y != 0, Z != 0)
/external/v8/src/arm/
Dconstants-arm.h395 RZ = 3 << 22, // Round towards zero. enumerator
401 kRoundToZero = RZ
Dsimulator-arm.cc3640 DCHECK((mode == RN) || (mode == RM) || (mode == RZ)); in get_inv_op_vfp_flag()
3665 case RZ: in get_inv_op_vfp_flag()
3724 case RZ: in ConvertDoubleToInt()
3761 : RZ; in DecodeVCVTBetweenFloatingPointAndInteger()
3762 DCHECK((mode == RM) || (mode == RZ) || (mode == RN)); in DecodeVCVTBetweenFloatingPointAndInteger()
4913 ConvertDoubleToInt(bit_cast<float>(q_data[i]), false, RZ)); in DecodeSpecialCondition()
4918 ConvertDoubleToInt(bit_cast<float>(q_data[i]), true, RZ)); in DecodeSpecialCondition()
/external/llvm/lib/Target/NVPTX/InstPrinter/
DNVPTXInstPrinter.cpp127 case NVPTX::PTXCvtMode::RZ: in printCvtMode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/InstPrinter/
DNVPTXInstPrinter.cpp133 case NVPTX::PTXCvtMode::RZ: in printCvtMode()
/external/v8/src/mips/
Dconstants-mips.h1149 RZ = 1 << 0, // Round towards zero. enumerator
1155 kRoundToZero = RZ,
1162 mode_trunc = RZ
/external/honggfuzz/examples/apache-httpd/corpus_http2/
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/external/v8/src/mips64/
Dconstants-mips64.h1183 RZ = 1 << 0, // Round towards zero. enumerator
1189 kRoundToZero = RZ,
1196 mode_trunc = RZ
/external/honggfuzz/examples/apache-httpd/corpus_http1/
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/external/ImageMagick/Magick++/demo/
Dmodel.miff64 5����uchhfcd:b4Q521//////GOadQ:[\RZ>45/&&&-EPOQ66(@KRLRVSH&
116 …�������������������������������� $+C^^^Z^NNCNX]_]SBCE@GbbcPRpvxvMKLRR\\RZ\\NQ(����������������…
/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp630 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate() local
633 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1); in evaluate()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp698 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate() local
701 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1); in evaluate()
/external/ImageMagick/PerlMagick/t/reference/filter/
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/external/ImageMagick/PerlMagick/t/reference/write/filter/
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