Searched refs:R_00B900_COMPUTE_USER_DATA_0 (Results 1 – 7 of 7) sorted by relevance
509 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in setup_scratch_rsrc_user_sgprs()577 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in si_setup_user_sgprs_co_v2()589 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in si_setup_user_sgprs_co_v2()600 R_00B900_COMPUTE_USER_DATA_0 + in si_setup_user_sgprs_co_v2()661 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); in si_upload_compute_input()677 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + in si_setup_tgsi_grid()
2107 unsigned base = R_00B900_COMPUTE_USER_DATA_0; in si_emit_compute_shader_pointers()2110 R_00B900_COMPUTE_USER_DATA_0); in si_emit_compute_shader_pointers()
3671 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0 in radv_emit_dispatch_packets()3734 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in radv_emit_dispatch_packets()
2084 return R_00B900_COMPUTE_USER_DATA_0; in radv_pipeline_stage_to_user_data_0()
1769 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); in radv_get_preamble_cs()
2616 #define R_00B900_COMPUTE_USER_DATA_0 0x00B900 macro
3819 #define R_00B900_COMPUTE_USER_DATA_0 0x00B900 macro