| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 124 // Operand: RdLo
157 // Operand: RdLo
224 // Operand: RdLo
257 // Operand: RdLo
|
| D | ARMGenMCCodeEmitter.inc | 4042 // op: RdLo
10299 // op: RdLo
10638 // op: RdLo
10669 // op: RdLo
10825 // op: RdLo
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3999 bits<4> RdLo;
4004 let Inst{15-12} = RdLo;
4011 bits<4> RdLo;
4016 let Inst{15-12} = RdLo;
4082 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4084 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4085 [(set GPR:$RdLo, GPR:$RdHi,
4090 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4092 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4093 [(set GPR:$RdLo, GPR:$RdHi,
[all …]
|
| D | ARMInstrThumb2.td | 543 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
544 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
546 bits<4> RdLo;
554 let Inst{15-12} = RdLo;
560 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
562 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
563 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
565 bits<4> RdLo;
573 let Inst{15-12} = RdLo;
2652 [(set rGPR:$RdLo, rGPR:$RdHi,
[all …]
|
| D | ARMInstrFormats.td | 907 bits<4> RdLo;
910 let Inst{15-12} = RdLo;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3836 bits<4> RdLo;
3841 let Inst{15-12} = RdLo;
3848 bits<4> RdLo;
3853 let Inst{15-12} = RdLo;
3914 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3916 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3919 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3921 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3924 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3925 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
[all …]
|
| D | ARMInstrThumb2.td | 542 bits<4> RdLo;
550 let Inst{15-12} = RdLo;
559 bits<4> RdLo;
567 let Inst{15-12} = RdLo;
2573 (outs rGPR:$RdLo, rGPR:$RdHi),
2575 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2578 (outs rGPR:$RdLo, rGPR:$RdHi),
2580 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2585 (outs rGPR:$RdLo, rGPR:$RdHi),
2587 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
[all …]
|
| D | ARMInstrFormats.td | 887 bits<4> RdLo;
890 let Inst{15-12} = RdLo;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3434 bits<4> RdLo;
3439 let Inst{15-12} = RdLo;
3497 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3499 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3502 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3504 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3507 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3508 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3511 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3514 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
[all …]
|
| D | ARMInstrThumb2.td | 473 bits<4> RdLo;
481 let Inst{15-12} = RdLo;
2344 (outs rGPR:$RdLo, rGPR:$RdHi),
2346 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2349 (outs rGPR:$RdLo, rGPR:$RdHi),
2351 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2356 (outs rGPR:$RdLo, rGPR:$RdHi),
2358 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2361 (outs rGPR:$RdLo, rGPR:$RdHi),
2363 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
[all …]
|
| D | ARMInstrFormats.td | 758 bits<4> RdLo;
761 let Inst{15-12} = RdLo;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 399 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $status",
401 def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$status),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 400 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch",
402 def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$scratch),
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 2302 IValueT RdLo = encodeGPRegister(OpRdLo, "RdLo", UmullName); in umull() local
2306 verifyRegNotPc(RdLo, "RdLo", UmullName); in umull()
2310 verifyRegsNotEq(RdHi, "RdHi", RdLo, "RdLo", UmullName); in umull()
2313 emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags); in umull()
|
| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 9003 // (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
9018 // (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
9214 // (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
9229 // (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
|