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Searched refs:Reg0 (Results 1 – 25 of 42) sorted by relevance

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/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DLocked.cpp86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
89 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
93 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
97 __ xchg(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
99 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
108 ASSERT_EQ(V1, test.Reg0()) << TestString; \ in TEST_F()
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
114 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
119 if (GPRRegister::Encoded_Reg_##Reg0 < 4 && \ in TEST_F()
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/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DLocked.cpp89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
92 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
96 __ mov(IceType_i##Size, Encoded_GPR_##Reg0(), Immediate(Value0)); \ in TEST_F()
98 __ xchg(IceType_i##Size, Encoded_GPR_##Reg0(), Encoded_GPR_##Reg1()); \ in TEST_F()
99 __ And(IceType_i32, Encoded_GPR_##Reg0(), Immediate(Mask##Size)); \ in TEST_F()
106 ASSERT_EQ(V1, test.Reg0()) << TestString; \ in TEST_F()
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
112 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
117 TestImplSize(Reg0, Reg1, 8); \ in TEST_F()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsTargetStreamer.h119 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
123 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
125 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
135 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
DMipsSEFrameLowering.cpp464 unsigned Reg0 = in emitPrologue() local
470 std::swap(Reg0, Reg1); in emitPrologue()
473 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
482 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
486 std::swap(Reg0, Reg1); in emitPrologue()
489 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/external/llvm/lib/Target/Mips/
DMipsTargetStreamer.h103 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
107 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
109 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
111 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
113 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
115 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
117 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
DMipsSEFrameLowering.cpp438 unsigned Reg0 = in emitPrologue() local
444 std::swap(Reg0, Reg1); in emitPrologue()
447 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
456 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
460 std::swap(Reg0, Reg1); in emitPrologue()
463 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp146 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
150 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
155 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
159 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
165 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
167 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
170 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
172 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
185 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
190 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp77 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction() local
84 if (HasDef && Reg0 == Reg1 && in commuteInstruction()
87 Reg0 = Reg2; in commuteInstruction()
88 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction()
91 Reg0 = Reg1; in commuteInstruction()
100 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstruction()
110 MI->getOperand(0).setReg(Reg0); in commuteInstruction()
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h613 uint16_t Reg0; variable
616 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
619 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
625 return Reg0;
630 return Reg0; in isValid()
636 Reg0 = Reg1;
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp129 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
133 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
138 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
142 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
148 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
150 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
155 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp241 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
242 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
246 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { in runOnMachineFunction()
248 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h642 uint16_t Reg0 = 0; variable
650 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
656 return Reg0;
661 return Reg0; in isValid()
667 Reg0 = Reg1;
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp243 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
244 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
248 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { in runOnMachineFunction()
250 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1861 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1881 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLD()
1884 Ops.push_back(Reg0); in SelectVLD()
1897 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
1910 Ops.push_back(Reg0); in SelectVLD()
1914 Ops.push_back(Reg0); in SelectVLD()
1991 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2036 Ops.push_back(Reg0); in SelectVST()
2040 Ops.push_back(Reg0); in SelectVST()
2065 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
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DThumb2SizeReduction.cpp706 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
712 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
715 if (Reg0 != Reg2) { in ReduceTo2Addr()
718 if (Reg1 != Reg0) in ReduceTo2Addr()
725 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
730 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
737 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1796 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1818 Ops.push_back(Reg0); in SelectVLD()
1821 Ops.push_back(Reg0); in SelectVLD()
1834 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
1847 Ops.push_back(Reg0); in SelectVLD()
1851 Ops.push_back(Reg0); in SelectVLD()
1930 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
1977 Ops.push_back(Reg0); in SelectVST()
1981 Ops.push_back(Reg0); in SelectVST()
2006 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
DThumb2SizeReduction.cpp736 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
742 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
745 if (Reg0 != Reg2) { in ReduceTo2Addr()
748 if (Reg1 != Reg0) in ReduceTo2Addr()
755 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
760 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
767 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelDAGToDAG.cpp1603 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1615 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLD()
1618 Ops.push_back(Reg0); in SelectVLD()
1631 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
1644 Ops.push_back(Reg0); in SelectVLD()
1648 Ops.push_back(Reg0); in SelectVLD()
1721 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
1757 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVST()
1761 Ops.push_back(Reg0); in SelectVST()
1786 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
248 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
263 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
248 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
263 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetInstrInfo.cpp165 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0; in commuteInstructionImpl() local
187 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
190 Reg0 = Reg2; in commuteInstructionImpl()
192 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
195 Reg0 = Reg1; in commuteInstructionImpl()
209 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp143 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0; in commuteInstructionImpl() local
157 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
160 Reg0 = Reg2; in commuteInstructionImpl()
162 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
165 Reg0 = Reg1; in commuteInstructionImpl()
179 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp1360 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1363 printRegName(O, Reg0); in printVectorListTwo()
1373 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1376 printRegName(O, Reg0); in printVectorListTwoSpaced()
1428 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1431 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1475 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1478 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp1476 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1479 printRegName(O, Reg0); in printVectorListTwo()
1489 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1492 printRegName(O, Reg0); in printVectorListTwoSpaced()
1544 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1547 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1591 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1594 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp219 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP() argument
226 .addReg(Reg0) in buildEXP()
263 unsigned Reg0 = I.getOperand(3).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
270 MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM, in selectG_INTRINSIC_W_SIDE_EFFECTS()

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