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Searched refs:Reg128 (Results 1 – 5 of 5) sorted by relevance

/external/boringssl/src/crypto/test/
Dabi_test.h51 struct alignas(16) Reg128 { struct
52 bool operator==(const Reg128 &x) const { return x.lo == lo && x.hi == hi; }
53 bool operator!=(const Reg128 &x) const { return !((*this) == x); }
76 CALLER_STATE_REGISTER(Reg128, xmm6) \ argument
77 CALLER_STATE_REGISTER(Reg128, xmm7) \
78 CALLER_STATE_REGISTER(Reg128, xmm8) \
79 CALLER_STATE_REGISTER(Reg128, xmm9) \
80 CALLER_STATE_REGISTER(Reg128, xmm10) \
81 CALLER_STATE_REGISTER(Reg128, xmm11) \
82 CALLER_STATE_REGISTER(Reg128, xmm12) \
[all …]
Dabi_test.cc305 memcpy(&state.xmm6, &ctx_.Xmm6, sizeof(Reg128)); in GetCallerState()
306 memcpy(&state.xmm7, &ctx_.Xmm7, sizeof(Reg128)); in GetCallerState()
307 memcpy(&state.xmm8, &ctx_.Xmm8, sizeof(Reg128)); in GetCallerState()
308 memcpy(&state.xmm9, &ctx_.Xmm9, sizeof(Reg128)); in GetCallerState()
309 memcpy(&state.xmm10, &ctx_.Xmm10, sizeof(Reg128)); in GetCallerState()
310 memcpy(&state.xmm11, &ctx_.Xmm11, sizeof(Reg128)); in GetCallerState()
311 memcpy(&state.xmm12, &ctx_.Xmm12, sizeof(Reg128)); in GetCallerState()
312 memcpy(&state.xmm13, &ctx_.Xmm13, sizeof(Reg128)); in GetCallerState()
313 memcpy(&state.xmm14, &ctx_.Xmm14, sizeof(Reg128)); in GetCallerState()
314 memcpy(&state.xmm15, &ctx_.Xmm15, sizeof(Reg128)); in GetCallerState()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td487 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
505 def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
539 def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {
545 def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {
551 def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {
557 def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {
563 def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {
569 def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {
575 def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {
581 def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td509 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
527 def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
561 def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {
567 def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {
573 def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {
579 def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {
585 def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {
591 def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {
597 def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {
603 def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp89 unsigned Reg128 = LowRegOp.getReg(); in splitMove() local
101 MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl); in splitMove()
102 MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed)); in splitMove()