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Searched refs:Reg2 (Results 1 – 25 of 75) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp454 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
465 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
467 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
473 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
476 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
484 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
490 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
493 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp511 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
522 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
524 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
527 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
530 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
533 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
536 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
541 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
547 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
550 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} in RegPairInfo()
876 unsigned Reg2; member
880 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
916 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
934 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
935 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
975 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
994 dbgs() << ", " << TRI->getName(Reg2); in spillCalleeSavedRegisters()
1003 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
1004 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)); in spillCalleeSavedRegisters()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp1143 unsigned Reg2 = AArch64::NoRegister; member
1150 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
1189 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
1194 if ((RPI.Reg1 == AArch64::LR || RPI.Reg2 == AArch64::LR) && in computeCalleeSaveRegisterPairs()
1216 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
1217 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
1273 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
1291 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI); in spillCalleeSavedRegisters()
1300 if (!MRI.isReserved(Reg2)) in spillCalleeSavedRegisters()
1301 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp409 bool &HaveReg2, Register &Reg2,
773 bool &HaveReg2, Register &Reg2, in parseAddress() argument
802 if (parseRegister(Reg2)) in parseAddress()
837 Register Reg1, Reg2; in parseAddress() local
841 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) in parseAddress()
876 if (parseAddressRegister(Reg2)) in parseAddress()
878 Base = Regs[Reg2.Num]; in parseAddress()
889 if (parseAddressRegister(Reg2)) in parseAddress()
891 Base = Regs[Reg2.Num]; in parseAddress()
913 if (parseAddressRegister(Reg2)) in parseAddress()
[all …]
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.h73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
DMipsAsmPrinter.cpp770 unsigned Reg2) { in EmitInstrRegReg() argument
779 Reg1 = Reg2; in EmitInstrRegReg()
780 Reg2 = Temp; in EmitInstrRegReg()
784 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
790 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
794 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
801 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
805 Reg1 = Reg2; in EmitMovFPIntPair()
806 Reg2 = temp; in EmitMovFPIntPair()
809 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp79 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() local
87 Reg0 = Reg2; in commuteInstruction()
88 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction()
101 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
105 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
112 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsAsmPrinter.h95 unsigned Reg1, unsigned Reg2);
98 unsigned Reg1, unsigned Reg2, unsigned Reg3);
101 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
DMipsAsmPrinter.cpp825 unsigned Reg2) { in EmitInstrRegReg() argument
834 Reg1 = Reg2; in EmitInstrRegReg()
835 Reg2 = Temp; in EmitInstrRegReg()
839 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
845 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
849 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
856 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
860 Reg1 = Reg2; in EmitMovFPIntPair()
861 Reg2 = temp; in EmitMovFPIntPair()
864 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
DMicroMipsSizeReduction.cpp372 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
382 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
401 unsigned Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
403 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
473 unsigned Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
475 if (Reg1 != Reg2) in ReduceXWtoXWP()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dnewvaluejump2.ll10 %Reg2 = alloca i32, align 4
11 %0 = load i32, i32* %Reg2, align 4
/external/llvm/test/CodeGen/Hexagon/
Dnewvaluejump2.ll10 %Reg2 = alloca i32, align 4
11 %0 = load i32, i32* %Reg2, align 4
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrBuilder.h84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { in addRegReg() argument
86 .addReg(Reg2, getKillRegState(isKill2)); in addRegReg()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.cpp620 CodeGenRegister *Reg2 = i1->second; in computeComposites() local
622 if (Reg1 == Reg2) in computeComposites()
624 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
631 if (Reg2 == Reg3) in computeComposites()
714 CodeGenRegister *Reg2 = getReg(RegList[i2]); in computeOverlaps() local
715 CodeGenRegister::Set &Overlaps2 = Map[Reg2]; in computeOverlaps()
716 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs(); in computeOverlaps()
718 Overlaps.insert(Reg2); in computeOverlaps()
/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp189 unsigned Reg2 = MI->getOperand(2).getReg(); in processBlock() local
191 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
192 && Reg2 != OldFMAReg) { in processBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp190 unsigned Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrBuilder.h117 unsigned Reg2, bool isKill2) { in addRegReg() argument
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCRegisterInfo.h85 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
86 return contains(Reg1) && contains(Reg2); in contains()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h145 unsigned Reg2, bool isKill2) { in addRegReg() argument
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrBuilder.h167 unsigned Reg2, bool isKill2) { in addRegReg() argument
169 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.cpp119 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstruction() local
139 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction()
143 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
150 MI->getOperand(0).setReg(Reg2); in commuteInstruction()
152 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetInstrInfo.cpp167 unsigned Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
182 bool Reg2IsRenamable = TargetRegisterInfo::isPhysicalRegister(Reg2) in commuteInstructionImpl()
190 Reg0 = Reg2; in commuteInstructionImpl()
192 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
213 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
226 if (TargetRegisterInfo::isPhysicalRegister(Reg2)) in commuteInstructionImpl()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h86 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
87 return MC->contains(Reg1, Reg2); in contains()
/external/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp710 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
713 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
715 if (Reg0 != Reg2) { in ReduceTo2Addr()
745 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
746 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()

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